Using topological and geometric routers to produce curvilinear routes

ABSTRACT

Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

BACKGROUND

An integrated circuit (“IC”) is a device that includes many electroniccomponents, such as transistors, resistors, diodes, etc. Thesecomponents are often defined on a semiconductor substrate andinterconnected with metal wiring and vias to form multiple circuitcomponents, such as gates, cells, memory units, arithmetic units,controllers, decoders, etc. An IC typically includes multiple layers ofwiring and vias that interconnect its electronic and circuit components.

SUMMARY

Some embodiments of the invention provide an integrated circuit (IC)that has a novel non-preferred direction (NPD) wiring architecture. Insome embodiments, the IC includes a substrate and multiple wiringlayers, which include a first set of one or more wiring layers with nopreferred wiring directions, and a second set of one or more wiringlayers with preferred wiring directions. In some embodiments, the firstset of wiring layers includes the third and fourth wiring layers, whilethe second set of wiring layers includes the fifth and higher metallayers with successive neighboring layers having different (e.g.,alternating) preferred wiring directions. The first set of wiring layersin other embodiments includes the third wiring layer but not the fourthwiring layer, which in these embodiments has a preferred wiringdirection. Also, the first and second wiring layers in some embodimentsbelong to the first set, while in other embodiments the first and secondwiring layers belong to the second set.

Each preferred wiring direction in some embodiments is a Manhattandirection (i.e., a horizontal direction or a vertical direction), withthe preferred wiring directions of different adjacent layers alternatingbetween horizontal and vertical directions. The preferred wiringdirections in other embodiments include other wiring directions (e.g.,45 or 60 degree wiring directions), with successive neighboring layershaving different preferred wiring directions. In some embodiments, thepreferred wiring direction on each layer is the direction that includesat least a certain threshold amount (e.g., 90% or 95%) of the wiring onthat layer. In some embodiments, the non-preferred direction wiring oneach layer of the first set of wiring layers includes interconnectwiring (also called wiring connection) that traverses in more than eightdirections.

In some embodiments, each layer of the first set of wiring layersincludes rectilinear wires (i.e., wires with only straight segments) andcurvilinear wires (i.e., wires with at least one curved segment). Insome embodiments, the first set of wiring layers of the IC is used forwire connections that are shorter than the wire connections defined onthe second set of wiring layers. In some embodiments, the first set ofwiring layers in some embodiments is used for short local connections,while the second set of wiring layers is used for longer connections.

The electronic design automation (EDA) tools (e.g., the router andcompactor) that define the design of the IC in some embodiments accountfor the preferred and non-preferred directions on each wiring layerwhile defining the routes that result in the metal wiring on theselayers. In some embodiments, when the first set of wiring layersincludes the third wiring layer and/or the fourth wiring layer, the EDAtools define NPD curvilinear routes for the third and/or fourth wiringlayers, but also define NPD curvilinear routes for the first and secondwiring layers. However, in some of these embodiments, the first andsecond wiring layers have preferred direction wiring in some of theirregions, such as the regions that are used for connections that areneeded to form the electronic components (e.g., the transistors) andcircuit blocks (e.g., IP blocks) that are defined on the IC’s substrateat locations below these regions. In some embodiments, the EDA tools usethe unused spaces on the first and second wiring layers to define NPDrectilinear and/or curvilinear routes, which result in NPDrectilinear/curvilinear wiring on the corresponding layers of themanufactured IC. The NPD rectilinear/curvilinear wiring on the first andsecond layers augments the NPD rectilinear/curvilinear wiring on thethird and/or fourth wiring layers.

In some embodiments, the first set of wiring layers of the IC is used toconnect any net that can be connected through wires on the first set ofwiring layers, while the second set of wiring layers is used to connectany nets that cannot be completely connected through wires on the firstset of wiring layers. In some of these embodiments, the design of the ICis based on rectilinear and curvilinear routes that are defined on thefirst N layers, where N is an integer greater than two, but onlyrectilinear routes on the next M layers of the IC, where M is anyinteger. Some embodiments allow rectilinear and curvilinear routes inthe IC design for not only some of the lower wiring layers but also forsome of the higher wiring layers (e.g., for all of the wiring layers, orfor the first few lower wiring layers and one or two of the top wiringlayers). In some embodiments, a rectilinear route is a route that onlyhas one or more straight line segments, while a curvilinear route is aroute with at least one curved segment.

In some embodiments, the interconnect connections on the first set ofwiring layers are defined with a NPD, curvilinear first router, whilethe interconnect connections on the second set of wiring layers aredefined by a preferred direction (PD) second router (e.g., a Manhattanrouter). The NPD first router produces routes on each layer in the firstset of wiring layers that traverse more than eight different directionson the layer. The first router in some embodiments also producescurvilinear routes on the first set of wiring layers. The PD secondrouter produces routes that on each layer in the second set of wiringlayers are predominantly along the preferred routing direction of thatlayer.

In some embodiments, the NPD first router defines a first set ofrectilinear and curvilinear routes traversing the first set of wiringlayers to connect a first set of node pairs that are within a thresholddistance of each other, while the PD second router defines a second setof rectilinear routes traversing the second set of wiring layers toconnect a second set of node pairs that are more than the thresholddistance from each other. Even though the first router in someembodiments can define both rectilinear and curvilinear routes, thesecond router in these embodiments does not produce any curvilinearroute, e.g., any route that has at least one curvilinear edge (i.e., acurved edge that is not a straight line).

Some embodiments first define the routes for the first set of wiringlayers of the IC design and then define the routes for the higher,second set of wiring layers of the IC design. For instance, someembodiments perform NPD detailed routing for the first set of wiringlayers without first performing global routing for these layers. Theseembodiments then perform global routing for the second set of wiringlayers, and after the global routing, perform detailed routing for thesecond set of wiring layers.

The NPD detailed routing of the first set of wiring layers in someembodiments does not use any preferred wiring directions. This NPDdetailed routing produces curvilinear routes as it allows all angle ofdirections to be explored during the path search operations of therouting, and then allows curvilinear edges to be used to define theroutes that are based on the completed path searches. In otherembodiments, the NPD detailed routing only produces rectilinear routesin a large, finite number of wiring direction, such as nine or morewiring directions, and does not produce designs with curvilinear routesegments. This is because in these embodiments, the path searches of therouting operation only explore expanding paths along the finite numberof wiring directions, and then use only rectilinear edges that are alongthese wiring directions to define the routes that are based on thecompleted path searches.

Also, in some embodiments, the NPD detailed router produces curvilinearroutes on a subset of layers in the first set of wiring layers (e.g., onthe first and second wiring layers) in between areas on these layersthat have PD rectilinear wiring that has been previously defined (e.g.,in regions on layers 1 and 2 that are used for the wiring of IP blocks).Accordingly, in these embodiments, these subset of lower wiring layershave regions with predefined PD rectilinear wiring, and areas betweenthese regions with NPD rectilinear and curvilinear wiring.

In some embodiments, the global and detailed routing for the PD wiringlayers uses Manhattan preferred directions, while in other embodimentsthe global and detailed routing for the PD wiring layers uses otherpreferred wiring directions (e.g., 45 or 60 degree wiring) conjunctivelyor alternatively with horizontal and vertical wiring direction. In someembodiments, the NPD wiring layers are the first set of wiring layers ofthe IC design, and the PD wiring layers are the second set of wiringlayers of the IC design. In other embodiments, the NPD wiring layersinclude the first two metal layers, the first three metal layers, or thefirst four metal layers of the IC design. In still other embodiments,the NPD wiring layers include additional metal layers as explainedabove.

In some embodiments, the NPD first set of wiring layers include firstand second subset of layers. In these embodiments, the method firstperforms a first detailed routing operation for the first subset oflayers (e.g., for the first or third wiring layer), and then aftercompleting the first detailed routing operation, performs a seconddetailed routing operation for the second subset of layers (e.g., forthe second or fourth wiring layer). The method in some embodimentsperforms the first and second detailed routing operations by using anNPD detailed router to perform the first detailed routing operation, andthen recursively calling the NPD detailed router to perform the seconddetailed routing operation.

The preceding Summary is intended to serve as a brief introduction tosome embodiments of the invention. It is not meant to be an introductionor overview of all inventive subject matter disclosed in this document.The Detailed Description that follows and the Drawings that are referredto in the Detailed Description will further describe the embodimentsdescribed in the Summary as well as other embodiments. Accordingly, tounderstand all the embodiments described by this document, a full reviewof the Summary, Detailed Description, the Drawings and the Claims isneeded. Moreover, the claimed subject matters are not to be limited bythe illustrative details in the Summary, Detailed Description and theDrawings.

BRIEF DESCRIPTION OF FIGURES

The novel features of the invention are set forth in the appendedclaims. However, for purposes of explanation, several embodiments of theinvention are set forth in the following figures.

FIG. 1 illustrates an IC with a novel non-preferred direction wiringarchitecture of some embodiments.

FIG. 2 illustrates example of curvilinear wires that are defined on thefirst and second layers of the IC, and horizontal and vertical wiresthat are defined on the third, fourth and fifth wiring layers of this ICin some embodiments.

FIG. 3 illustrates another example of an IC that uses the novel NPDwiring architecture of some embodiments.

FIG. 4 illustrates an example of wires on the first two layers that cantraverse in only 16 possible rectilinear directions.

FIG. 5 illustrates an IC that uses 45 degree PD wiring on the sixth andseventh metal layers of the IC.

FIG. 6A illustrates an example of an IC that has predominantly shortedwires on the first and second metal layers and predominantly longerwires on the fifth metal layer.

FIG. 6B illustrates an example of an IC that has NPD curvilinear wiringon the first, second and third metal layers and PD wiring on fourth andfifth metal layers.

FIG. 6C illustrates an example of an IC that has NPD curvilinear wiringon the first, second, third and fourth metal layers and PD wiring onfifth and higher metal layers.

FIG. 6D illustrates an example of an IC that has NPD rectilinear andcurvilinear wiring on the third and fourth wiring layers and, inaddition, rectilinear and curvilinear wiring on the first and secondwiring layers in areas that are not occupied for PD wiring on theselayers.

FIG. 7 illustrates an example of an IC where all of its metal layers areNPD metal layers that have all angle rectilinear wiring and curvilinearwiring.

FIG. 8 illustrates a routing process that defines routes to connect anet list associated with a design of an IC.

FIG. 9 illustrates a routing process of some embodiments that only usesdetailed routing to define routes for NPD wiring layers, and then usesglobal routing and detailed routing to define routes for the PD wiringlayers.

FIG. 10 illustrates an NPD detailed routing process of some embodiments.

FIG. 11 illustrates two boundary crossings for the same net that aredefined by two different detailed router instances that define NPDroutes for the two neighboring partitions.

FIG. 12 illustrates an example of a constraint defined.

FIG. 13 illustrates an example of another approach used by someembodiments to use route crossing data specified by one detailed routerof one partition with the detailed router of a neighboring partition.

FIG. 14 illustrates another NPD detailed routing process of someembodiments.

FIG. 15 illustrates a process for manufacturing ICs with curvilinearroutes according to some embodiments.

FIG. 16 illustrates an example of the five wiring layers of an IC designproduced by one or more physical design tools of some embodiments.

FIG. 17 illustrates another example of a metal layer of an IC designthat is defined to have curvilinear route segments.

FIGS. 18 and 19 illustrate examples of two routing processes that definecurvilinear, NPD routers in a way that reduces the number of vias.

FIG. 20 illustrates an example of a set of nets that need to beconnected through routes.

FIG. 21 illustrates an example of traditional Manhattan routes on metallayers 3 and 4 that connect the pins of each of several nets illustratedin FIG. 20 .

FIG. 22 illustrates an example of curvilinear, NPD routes on metallayers 3 and 4 that connect the pins of each of several nets illustratedin FIG. 20 .

FIG. 23 illustrates an example of an NPD router of some embodiments.

FIG. 24 illustrates an example of a geometric router in some embodimentsthat uses a machine learning engine to identify geometric routes for aset of nets for which a topological router identifies topologicalroutes.

FIG. 25 illustrates an example of a topological router that tessellatesa partition into 64 rectangular cells, which it then uses to definetopological routes.

FIGS. 26 and 27 illustrate two alternative processes for defining apartition size that is related to the amount of compute and memoryresources of a computer.

FIG. 28 conceptually illustrates an electronic system with which someembodiments of the invention are implemented.

DETAILED DESCRIPTION

In the following detailed description of the invention, numerousdetails, examples, and embodiments of the invention are set forth anddescribed. However, it will be clear and apparent to one skilled in theart that the invention is not limited to the embodiments set forth andthat the invention may be practiced without some of the specific detailsand examples discussed.

Some embodiments of the invention provide an integrated circuit (IC)that has a novel non-preferred direction (NPD) wiring architecture. Insome embodiments, the IC includes a substrate and multiple wiringlayers, which include a first set of one or more wiring layers with nopreferred wiring directions, and a second set of one or more wiringlayers with preferred wiring directions. In some embodiments, the firstset of wiring layers includes the third and fourth wiring layers, whilethe second set of wiring layers includes the fifth and higher metallayers with successive neighboring layers having different (e.g.,alternating) preferred wiring directions. The first set of wiring layersin other embodiments includes the third wiring layer but not the fourthwiring layer, which in these embodiments has a preferred wiringdirection. Also, the first and second wiring layers in some embodimentsbelong to the first set, while in other embodiments the first and secondwiring layers belong to the second set.

Each preferred wiring direction in some embodiments is a Manhattandirection (i.e., a horizontal direction or a vertical direction), withthe preferred directions (PDs) of different adjacent layers alternatingbetween horizontal and vertical directions. The preferred wiringdirections in other embodiments include other wiring directions (e.g.,45 or 60 degree wiring directions), with successive neighboring layershaving different preferred wiring directions.

In some embodiments, the preferred wiring direction on each layer is thedirection that includes at least a certain threshold amount (e.g., 90%or 95%) of the wiring on that layer. In some embodiments, thenon-preferred direction wiring on each layer of the first set of wiringlayers includes wiring (also called interconnects, interconnect lines,wires or wire segments below) that traverses along more than eightdirections. In some embodiments, each layer of the first set of wiringlayers includes curvilinear wires, i.e., wires with at least one curvedsegment. A curved segment is a segment that is not a straight line butrather is curved.

The electronic design automation (EDA) tools (e.g., the router andcompactor) that define the design of the IC in some embodiments accountfor the preferred and non-preferred directions on each wiring layerwhile defining the routes that result in the metal wiring on theselayers. Some embodiments employ both PD and NPD EDA routers. The PD EDArouters in some embodiments penalize route segments that traverse alongthe non-preferred wiring directions on particular wiring layers whilenot penalizing route segments that traverse along the preferred wiringdirections on the particular wiring layers (e.g., assesses a wirelengthcost for route segments traversing along the preferred wiring direction,while assessing a wirelength cost and a penalty cost for route segmentstraversing along the non-preferred wiring directions). By penalizingroute segments traversing along non-preferred directions, the EDArouters ensure that more than a threshold amount (e.g., 90% or 95%) ofthe routes on a PD wiring layer are along the preferred wiring directionof that layer.

In some embodiments, the NPD routers define routes on the first set ofwiring layers of the IC design. Unlike the PD routers, the NPD routersin some embodiments do not penalize routing in any particular directionon a wiring layer in the first set, and hence do not produce designs inwhich more than a threshold amount (e.g., 90% or 95%) of the routes onthe NPD wiring layer are along any preferred wiring direction. In otherwords, the NPD routers in some embodiments do not penalize routes thatare along any rectilinear or curvilinear directions, in order to createa bias towards eight or fewer preferred wiring directions on a layer.

In some embodiments, the NPD routers do not penalize routing along a setof nine or more specific wiring directions but do penalize routing alongone or more wiring directions that are not in the set of non-penalizedwiring directions. In some embodiments, an NPD router (or an NPD routingoperation) defines curvilinear routes and/or rectilinear routes thattraverse in more than eight wiring directions on a wiring layer, while aPD router (or a PD routing operation) does not define any curvilinearroutes and only defines rectilinear routes. Several examples of such PDand NPD routers and routing operations are further described below.

In some embodiments, a rectilinear route is a route that only has one ormore straight line segments (also referred to as straight line edges),while a curvilinear route is a route with at least one curved segment(also referred to as a curved edge). A preferred direction (PD)rectilinear route in some embodiments is a route that has itsstraight-line segments on each layer traverse along the PD of thatlayer. In other embodiments, a PD rectilinear route is a route that hasthe majority of its straight line segments on each layer traverse alongthe PD of that layer.

FIG. 1 illustrates an IC 100 with a novel non-preferred direction wiringarchitecture of some embodiments. As shown, the IC 100 includes asubstrate 105 and multiple wiring layers (also called metal layers). Thewiring layers include first and second wiring layers 102 and 104 thathave no preferred wiring directions, and third, fourth and fifth wiringlayers 106, 108 and 110 that have first, second and third preferreddirections (PDs) respectively. As such, the first and second layers donot have wire segments that predominantly traverse along one direction(e.g., do not have more than 90% of the wire segments traverse along onedirection), while the third, fourth and fifth layers have their wiresegments predominantly traverse (i.e., have more than 90% or 95% oftheir wires traverse) along the respective preferred wiring direction ofthese layers.

In FIG. 1 , the preferred wiring directions of different adjacent PDwiring layers alternate between horizontal and vertical directions,i.e., the third wiring layer 106 has a horizontal preferred direction,the fourth wiring layer 108 has a vertical preferred direction and thefifth wiring layer 110 has a horizontal preferred direction wiring. TheIC 100 in some embodiments further includes metal layer 0, as well asmultiple other metal layers (e.g., sixth, seventh, and eighth metallayers). Metal layer 0 is the substrate layer in some embodiments or thefirst layer above the substrate layer in other embodiments.

FIG. 2 illustrates examples of curvilinear wires 200 that are defined onthe first and second layers 102 and 104 of the IC 100, and horizontaland vertical wires 205 and 210 that are defined on the third, fourth andfifth wiring layers 106, 108 and 110 of this IC. In some embodiments,numerous electronic components (e.g., active components, liketransistors and diodes, or passive components, like resistors andcapacitors) are defined on the IC substrate, and these electroniccomponents are connected to each other through interconnect wiring(e.g., wires 200, 205, and 210) on the wiring layers (e.g., layers102-110 of IC 100) to form numerous microcircuits (e.g., Boolean gates)and/or larger circuits (e.g., functional blocks).

As such, the wires 200, 205, and 210 on the metal layers 102-110 aredefined to electrically connect circuit nodes (e.g., points, contacts,terminals or regions of a circuit element or between two circuitelements of circuits) in order to form electrical components (e.g.,transistors, diodes, etc.) and circuits. Wires on different metal layersare connected through one or more vias (not shown) in order to establisha contiguous electrical connection to connect two different nodesthrough wires that traverse different metal layers. Such a contiguouselectrical connection can be viewed as a multi-layer wire orinterconnect that traverses multiple wiring layers to connect twodifferent electrical nodes of the IC.

As shown in FIG. 2 , the first and second metal layers 102 and 104 havestraight wire 201 and curved wire 200 that traverse in any possibledirection. In some embodiments, the wires on these layers can traversein any possible angle as these layers have no preferred wiringdirections. Also, as depicted by curvilinear wire 200 a on the firstmetal layer, one curvilinear wire can be formed by one or more straightwire segments and one or more curved wire segments on the metal layer. Acurved wire segment in some embodiments is a segment that has a shapedefined by a nonlinear equation. Also, in some embodiments, a curvedwire segment is a continuously smooth wire segment that bends withoutthe use of sharp angles.

Unlike the first and second metal layers 102 and 104, the third, fourthand fifth metal layers 106, 108 and 110 have preferred wiring directionsand have wiring interconnects that traverse mostly in their preferredwiring directions, e.g., the third metal layer has mostly horizontalwires, the fourth metal layer has mostly vertical wires, and the fifthmetal layer has mostly horizontal wires. A PD wiring layer can havewires that traverse in non-preferred directions. Accordingly, as shownin FIG. 2 and other figures described below, each PD wiring layer isshown to have a small amount of wires that traverse in non-preferreddirections. These NPD wire segments on PD wiring layers are depicted inFIG. 2 and other figures as occasional small diagonal or Manhattan jogson these layers in the non-preferred directions. These jogs can occur atthe wire ends on a metal layer, or can occur in between two other wiresegments on a metal layer. The Manhattan jogs that are defined in an ICdesign can result in curvilinear segments on the PD wiring layers of themanufactured IC as a result of manufacturing limitations.

FIG. 3 illustrates another example of an IC 300 that uses the novel NPDwiring architecture of some embodiments. Like IC 100 of FIG. 1 , the IC300 has NPD wiring on the first and second layers 302 and 304, andtraditional Manhattan PD wiring on its third, fourth and fifth layers306, 308 and 310. However, unlike IC 100, the IC 300 only has straightwires defined on its first two layers 302 and 304. In other words, theEDA tools that define the wiring on these two layers did not definecurvilinear wires on these layers and instead define only straight wiresto traverse these layers 302 and 304. Manufacturing constraints mightresult in small curvilinear segments being inadvertently formed at theangled junctions between wire segments, but the EDA tools do notintentionally define such curvilinear segments.

In this example, the wires on the first two layers 302 and 304 traversein all possible rectilinear directions (i.e., traverse in any anglebetween 0 to 360). In other embodiments, the wires on the NPD wiringlayers (such as the first and second layers of FIG. 3 ) do not traversein all possible rectilinear directions but rather traverse in a largenumber of rectilinear directions (e.g., ten, sixteen, twenty or largernumber of rectilinear directions). For instance, FIG. 4 illustrates anIC 400 that is similar to the IC 300 of FIG. 3 , except that the wireson the first two layers 402 and 404 can traverse in only 16 possiblerectilinear directions (i.e., 0, 30, 45, 60, 90, 120, 135, 150, 180,210, 225, 240, 270, 315, 330, and 360 degrees).

Other embodiments use other preferred direction wiring for the PD wiringlayers, such as the third, fourth and fifth wiring layers of FIGS. 1-4 .FIG. 5 illustrates an IC 500 that is like the IC 100 of FIG. 1 , exceptthat it uses 45 degree PD wiring on the sixth and seventh metal layers502 and 504 of the IC. The sixth layer 502 has 45 degree PD wiring,while the seventh layer 504 has -45 degree PD wiring. Still otherembodiments use other preferred directions on the metal layers with thePD wiring (e.g., use 60 degree wiring). In some embodiments, the NPDwiring layers of the IC (e.g., first and second wiring layers 102 and104 of the IC 100) are predominantly used for short local connections,while the PD wiring layers are predominantly used (e.g., the third,fourth and/or fifth wiring layers 106, 108, and 110) are used for longerconnections.

FIG. 6A illustrates an example of an IC 600 that has predominantlyshorter wires on the first and second wiring layers 102 and 104 forfacilitating local connections between the underlying circuit nodes, anduses predominantly longer wires on the fifth wiring layer 110 for longerconnections between the circuit nodes. The third and fourth wiringlayers 106 and 108 in this example have a combination of shorter lengthwires, intermediate length wires and longer wires. The shorter wires onthese layers 106 and 108 are used to connect nearby circuit nodes thatcannot be connected through wiring on the NPD wiring layers 102 and 104due to congestion on these layers. The wires on one metal layer (e.g.,the shorter wires on the third layer 106) connects to wires on othermetal layers (e.g., wires on the first and second layers 102 and 104)through vias to form contiguous electrical connections to connectcircuit nodes.

In some embodiments, the router that defines the wiring on the metallayers of the IC 600 defines rectilinear and curvilinear wires for thefirst and second wiring layers of the EDA design of the IC 600. For allother metal layers, the router only defines rectilinear routes, whichmay occasionally have Manhattan or diagonal jogs that when manufacturedappear as curvilinear jogs. Notwithstanding these occasional,unintentional curvilinear jogs, the IC 600 does not have as manycurvilinear wire segments on metal layers 3 and above as it does onmetal layers 1 and 2.

This is not the case in other embodiments. For instance, in someembodiments, the router employs a wiring model in which the third wiringlayer is the wiring layer that predominantly uses NPD curvilinearwiring. FIG. 6B illustrates an example of an IC 625 that had its designdefined by EDA tools (e.g., routers) that used NPD curvilinear wiring onthe first, second and third wiring layers 102, 104 and 606. In otherembodiments, the router employs a wiring model in which the third andfourth wiring layers are the wiring layers that predominantly use NPDcurvilinear wiring. FIG. 6C illustrates an example of an IC 650 that hadits design defined by EDA tools (e.g., routers) that used NPDcurvilinear wiring on the first, second, third, and fourth wiring layers102, 104, 606 and 608.

For both the scenarios illustrated in FIGS. 6B and 6C, the routers ofsome embodiments not only define rectilinear and curvilinear NPD routeson the third wiring layer, or the third and fourth wiring layers, butalso define rectilinear and curvilinear NPD routes on the first andsecond wiring layers. However, in some embodiments, the first and secondwiring layers are entirely open during routing for rectilinear orcurvilinear NPD routes.

In other embodiments, the first and second wiring layers are notentirely open during routing for rectilinear or curvilinear NPD routes.For instance, the first two wiring layers in some embodiments haveregions that are used for rectilinear or diagonal PD wiring. Theseregions, for example, include regions used by wires that connect circuitblocks (e.g., the IP blocks) that are typically defined on the substrateat locations below these regions. Hence, in such embodiments, the NPDrouters not only define rectilinear and curvilinear NPD routes on thethird wiring layer, or the third and fourth wiring layers, but alsoopportunistically define rectilinear and curvilinear NPD routes in theunused spaces on the first and second wiring layers that are not usedfor the PD wiring that is needed to define the circuit blocks (e.g., theIP blocks) of the IC.

In still other embodiments, the first and second wiring layers only havePD wiring as they are only routed by PD routers. In these embodiments,the only wiring layers that are NPD wiring layers are the layers abovethe first and second wiring layers. For instance, in some embodiments,the third and fourth wiring layers are NPD wiring layers with NPDrectilinear and curvilinear wires, while all other layers are PD wiringlayers with PD rectilinear wires. In addition to the third and fourthwiring layers, the IC and IC design of other embodiments have one ormore other higher wiring layers as NPD wiring layers with NPDrectilinear and curvilinear wires.

FIG. 6D illustrates one such example. This figure illustrates an IC 675that has NPD rectilinear and curvilinear wiring on the third and fourthwiring layers 624 and 626 that were designed using NPD routing for theentirety of the third and fourth wiring layers. In addition to these NPDwiring layers, the IC 675 has NPD rectilinear and curvilinear wiring onthe first and second wiring layers 620 and 622 in areas that are notoccupied for PD wiring on these layers. As shown, the first wiring layer620 has three regions 680, 682, and 684 with PD wiring, while the secondwiring layer 622 has two regions 686 and 688 with PD wiring. As furthershown, the IC 675 has NPD rectilinear and curvilinear wiring in the restof areas on the first and second wiring layers 620 and 622 that falloutside of the regions 680-688. In some embodiments, the NPD router thatdefines the NPD routes on the third and fourth wiring layers 624 and 626also opportunistically defines NPD rectilinear and curvilinear routes inthe areas on the first and second wiring layers 620 and 622 that are notused for the PD wiring of the IC’s circuit blocks.

In some embodiments, the NPD router uses the lower NPD wiring layers(i.e., the first through fourth wiring layers) predominantly for shortlocal connections, while using the higher PD wiring layers (i.e., thefifth and higher wiring layers) predominantly for longer connections.The NPD router in some of these embodiments uses the first and secondwiring layers for very short connections that can start and end in onecontiguous unused space on one or both of these wiring layers, and thenuses the third and fourth wiring layers for short connections thatcannot be made by using one contiguous unused space on the first andsecond wiring layers. In some embodiments, the first and second wiringlayers have many more PD wiring regions than those illustrated in FIG.6D as the IC has many more IP blocks that use such PD wiring on the IC’slower wiring layers. Also, in some embodiments, the IP blocks use PDwiring on other metal layers (e.g., the third and/or fourth metallayers).

In FIGS. 6A-6D, the ICs have PD wiring on the higher metal layers suchthat after the last NPD metal layer, all subsequent metal layers have PDwiring. This is not the case in other embodiments. For instance, the ICof some embodiments has one or more of its highest metal layers and oneor more of its lowest metal layers as NPD metal layers, while having PDmetal layers between these highest and lowest NPD metal layers. The NPDmetal wiring on these highest and lowest metal layers are manufacturedin some embodiments based on NPD rectilinear or curvilinear routes thatNPD routers define on the wiring layers (of the EDA design)corresponding to these metal layers. In one such embodiment, the IC hasexterior pins defined above its last metal layer, and the top NPD metallayer uses NPD rectilinear and curvilinear wiring (defined based onrectilinear and curvilinear NPD routes) as the most optimalinterconnects (e.g., shortest length and/or shortest delay wiring) toconnect the exterior pins to via locations on the top layer, to allowsignals to quickly traverse down or up the metal layers from or to thepins.

FIG. 7 illustrates another example of an IC with NPD metal layers beyondthe first through fourth metal layers. In this figure, the IC 700 issimilar to the IC 600 except that all of its metal layers are NPD metallayers that have all angle rectilinear wiring and curvilinear wiring.Like IC 600 of FIG. 6A, the IC 700 has predominantly shorter wires onthe first and second wiring layers 102 and 104 for facilitating localconnections between the underlying circuit nodes, and has longer wireson its third, fourth and fifth wiring layer 706, 708 and 710. The fifthwiring layer 710 has longer wires, while the third and fourth wiringlayers 706 and 708 have a combination of shorter length wires,intermediate length wires and longer wires.

In FIG. 7 , the shorter wires on the third and fourth layers are used toconnect nearby circuit nodes that cannot be connected through the wiringon the first and second wiring layers 102 and 104 due to congestion onthese layers. Also, the wires on one metal layer (e.g., the shorterwires on the third layer 706) connects to wires on other metal layers(e.g., wires on the first and second layers 102 and 104) through vias toform contiguous electrical connections to connect circuit nodes.

As mentioned above, some embodiments use several EDA tools to define theIC designs that when manufactured result in the ICs illustrated in FIGS.1-7 . These EDA tools base their operations on wiring models that definePD and/or NPD rectilinear wiring and/or curvilinear wiring for eachwiring layer of the IC design. For some embodiments, the wiring modelsillustrated for the ICs in FIGS. 1-7 correspond to the wiring modelsthat the EDA tools use when they design the ICs.

The IC in some embodiments includes several multi-layer interconnectjunctions to enable interconnect wiring to traverse from the lowercurvilinear non-preferred direction wiring layers (e.g., first andsecond wiring layers) to the higher, preferred direction wiring layers(e.g., third and fourth wiring layers). The multi-layer interconnectjunctions in some embodiments are positioned on the IC according to aparticular arrangement, such as an array. Each multi-layer interconnectjunction in some embodiments includes several vias that connect acurvilinear non-preferred direction wiring layer (e.g., one of the firstand second layers) to a preferred direction wiring layer (e.g., one ofthe third and fourth layers). Each such conjunction in some embodimentsalso includes vias that connect two curvilinear non-preferred directionwiring layers and/or two preferred direction wiring layers.

The IC in some embodiments includes several buffers that are definedwithin a threshold distance from each of several multi-layerinterconnect junctions. These buffers are used to drive signals onlonger interconnect wiring on the preferred direction wiring layers(e.g., the third and fourth wiring layers). The IC in some embodimentsalso includes several buses on the first wiring layer and/or secondwiring layer, with each bus allowing interconnect connections on firstand second wiring layers to circumvent at least one multi-layerinterconnect junction.

In some embodiments, the wiring connections on lower NPD wiring layers(such as third and fourth layers, or first to fourth layers) are definedwith a NPD first router, while the wiring connections on the upper PDwiring layers (such as layer five and higher) are defined by a PD secondrouter (e.g., a Manhattan router). The NPD first router produces routeson each of the lower layers that traverse more than eight differentdirections on each of these layers. The first router in some embodimentsalso produces curvilinear routes on the lower wiring layers. The use ofsuch routers is further described below.

FIG. 8 illustrates a routing process 800 that defines routes to connecta net list associated with a design of an IC. A netlist identifiesseveral nets, with each net corresponding to two or more nodes in the ICdesign that need to be connected by one or more routes. As shown, theprocess 800 uses (at 805) a first non-preferred direction router todefine routes on a lower first set of wiring layers, and uses (at 810) asecond preferred-direction router to define routes on a higher secondset of wiring layers. In some embodiments, the second router (used at810) is one of the commercially available routers sold today, e.g.,routers sold by Cadence, Inc. or Synopsys, Inc.

In some embodiments, the first set of wiring layers include the firstand second wiring layers while the second set of one or more wiringlayers include the third to seventh wiring layers. In other embodiments,the first set of wiring layers includes first to third wiring layerswhile the second set includes fourth to seventh wiring layers. In stillother embodiments, the first set of wiring layers includes first throughfourth wiring layers while the second set includes fifth to seventhwiring layers.

As mentioned above, the first and second wiring layers in someembodiments include PD wiring (e.g., Manhattan wiring) for circuitblocks (e.g., IP blocks) used on the IC design. In these embodiments,the NPD router uses the space available on the first and second wiringlayers to define NPD routes (e.g., rectilinear or curvilinear NPDroutes), and also uses the third metal layer, and fourth metal layerwhen the fourth layer is available for NPD wiring, to define NPD routes.

In other embodiments, the first set of wiring layer includes only thethird wiring layer or the third and fourth wiring layers, and do notinclude the first and second wiring layers. In some embodiments, onlyone or more of the lower wiring layers are used to define NPDrectilinear or curvilinear routes. Other embodiments, on the other hand,allow one or more of the top wiring layers to be used to define NPDroutes, as further mentioned above.

Also, in some embodiments, the first router (used at 805) is formed bytwo routing components, a topological router and a geometric router. Atopological router in some embodiments tessellates each IC design layerinto several polygons (also called faces), and then defines topologicalroutes (to connect nets) by reference to the edges of the tessellatedlayers. A particular topological route has its position defined in termsof its relative position with respect to other topological routes alongthe edges crossed by the particular topological route. The topologicalrouter of some embodiments also uses nodes associated with faces of thepolygons to model vias between wiring layers traversed by topologicalroutes. In these embodiments, the topological routes are defined by notonly the edge but also the face nodes and their relative position withrespect to each other by reference to these edges and face nodes.

In some embodiments, each particular topological route is also definedby the coordinates of a pair of nodes (of the netlist) connected by thetopological route, or just by reference to the pair of nodes as thestarting and ending point of the topological route. This specificstarting and ending points of a topological route differentiates atopological route from a global route. Also, another feature thatdifferentiates a topological route from a global route is that thetopological route has segments (defined by references to tessellatededge crossings) that are associated with specific wiring layers (e.g.,different segments of a topological route in some embodiments can be ondifferent wiring layers). Global routes, on the other hand, can bedefined without reference to particular wiring layers crossed by thoseroutes.

The geometric router in some embodiments then defines a geometricrealization for each topological route by snapping the topological routeto a grid (imposed on the wiring layers) along the allowed wiringdirections for the layer. In the embodiments that allow curvilinearsegments, this snapping allows for wire segments to be curvilinear. Insome embodiments, a topological route does not have any width orspecific coordinates for its segments, other than the coordinates of thetwo nodes (e.g., two pins) connected by the topological route. Insteadof snapping each topological route to a grid, the geometric router insome embodiments defines a width for each topological route, and thenleaves it to a subsequent compactor to geometrize fully the route (e.g.,to produce a full geometric definition of the route). In some suchembodiments, the geometric router defines for each topological routesome intermediate coordinates for the route so that the geometric routethat it produces for the topological route not only has some width butalso has one or more intermediate coordinates that define two or moreroute segments. One topological route can have many different geometricrealizations (i.e., one topological route can be associated with manygeometric routes).

In some embodiments, the routes on the non-preferred direction lowerwiring layers traverse in more than eight directions (e.g., 20, 90, 180,360, etc. directions). These routes on some or all of the lower layersare all rectilinear (e.g., the first two wiring layers) in someembodiments, while the routes on all of the lower layers (e.g., thefirst four wiring layers) include curvilinear and rectilinear routes inother embodiments.

In some embodiments, the routes defined by the first router connect nodepairs that are within a threshold distance of each other, while theroutes defined by the second router connect node pairs that are morethan the threshold distance from each other. To connect the node pairsthat are more than a threshold distance from each other, the routingprocess 800 uses both the first and second routers, e.g., uses the firstrouter to define the route segments that traverse along the lowernon-preferred direction wiring layers, and uses the second router todefine the route segments that traverse along the upper preferreddirection wiring layers. To facilitate the operation of the secondrouter in cases where the second router has to complete a route that ispartially completed by the first router, the first router in someembodiments defines one or more of its NPD route segments on the firstset of wiring layers up to locations used on these layers to via to thesecond set of wiring layers. The second router then commences itsrouting operations from these via locations in order to complete theroutes that were only partially completed by the first router.

Some embodiments first define the routes that traverse the lower firstset of wiring layers of the IC design and then define the routes thattraverse the higher wiring layers of the IC design. For instance, someembodiments perform global routing, and then perform a first NPDdetailed routing followed by a second PD detailed routing. Otherembodiments perform NPD detailed routing for the lower first set ofwiring layers of the IC design without first performing global routingfor these layers. These embodiments then perform PD global routing, andafter the global routing, perform PD detailed routing to define PDroutes that use the higher second set of wiring layers of the IC design.

The NPD detailed routing in some embodiments does not restrict its pathsearch processes to search only one or more preferred wiring directionsor penalize the other wiring directions on the first set of wiringlayers. On this set of wiring layers, the NPD detailed routing in someembodiments produces curvilinear routes as it allows its path search toexplore any angle for its route expansion, and then subsequentlygeometrized through the use of curvilinear wire segments. In otherembodiments, the NPD detailed routing only explores path searches in alarge, finite number of wiring direction, such as nine or more wiringdirections, and does not produce designs with curvilinear routesegments.

In some embodiments, the global and detailed routing for the PD wiringlayers uses Manhattan preferred directions, while in other embodimentsthe global and detailed routing for the PD wiring layers uses otherpreferred direction wiring (e.g., 45 or 60 degree wiring instead of orin conjunction with horizontal and vertical direction wiring). In someembodiments, the first set of wiring layers include the first two metallayers of the IC design, and the second set of wiring layers are metallayers three and higher of the IC design. In other embodiments, thefirst set of wiring layers include more than the first two metal layersof the IC design, e.g., include layers 1 to 4.

In some embodiments, the first set of wiring layers include first andsecond subset of layers (e.g., includes the third wiring layer and thefourth wiring layer). In these embodiments, the method performs thedetailed routing for the first set of wiring layers by performing afirst detailed routing operations for the first subset of layers (e.g.,for the third wiring layer), and after completing the first detailedrouting operation, performing a second detailed routing operation forthe second subset of layers (e.g., for the fourth wiring layer). Themethod in some embodiments performs the first and second detailedrouting operations by using an NPD detailed router to perform the firstdetailed routing operation, and then recursively calling the NPDdetailed router to perform the second detailed routing operation.

FIG. 9 illustrates a routing process 900 of some embodiments that onlyuses detailed routing to define NPD routes for a number of nets on afirst set of lower wiring layers, and then uses global routing anddetailed routing to define PD routes for the remaining nets on the firstset of lower wiring layers and a second set of higher wiring layers. Asshown, the process 900 starts by performing (at 905) NPD detailedrouting for several nets on the lower first set of wiring layers of theIC design without first performing global routing for these nets on thelower first set of wiring layers. As further described below byreference to FIG. 10 , the NPD detailed routing operation (at 905) triesto connect as many nets as possible through wire segments on the firstset of wiring layers (e.g., the first three metal layers or the firstfour metal layers).

To do this NPD routing, the process 900 sorts the nets based on theestimated length of routes for connecting each net (i.e., based on theestimated wirelength for connecting each net). Examples of usingheuristics to compute estimated wire lengths for the nets are providedbelow by reference to FIG. 18 . The sorted order is an ascending orderwith the nets having the shorter estimated lengths higher on the orderthan the nets with longer estimated lengths. Based on this order, theNPD routing process iteratively selects as many nets as possiblestarting at the top of the order with the shorter nets, and tries todefine NPD routes for the selected nets on the lower first set of wiringlayers. The NPD detailed routing operation in some embodiments does notexplore routes that use wire segments on the second set of higher wiringlayers (e.g., the fifth and higher metal layers). In some embodiments,the second set of higher wiring layers is reserved for the PD detailedrouting that is performed at 915, as further described below.

In some embodiments, the NPD detailed routing explores all-angle ofwiring directions as it does not use any preferred wiring directions. Onthe first two layers, the NPD detailed routing explores the all-anglewiring in spaces that are not occupied on these layers for the circuitblocks that have predefined wiring, such as IP blocks that come withpredefined PD wiring in some embodiments.

In some embodiments, the NPD detailed routing produces curvilinearroutes as it explores curvilinear directions during its path searches.Alternatively, in some embodiments, the NPD detailed routing producescurvilinear routes because after its topological router identifies atopological route by reference to several tessellated edges and faces,the geometric router embeds the topological route as a geometric routewith one or more rectilinear route segments and/or curvilinear routesegments, based on whichever is more optimal. In some embodiments, thegeometric router only defines an initial geometric route for eachtopological route, and leaves the final definition of the geometricroute for a post-processing operation, such as a compaction operationthat follows. As further described below, the post-processing operationin some embodiments defines the geometric routes based on one or morecriteria, such as compacting the design to reduce the overall die size,or spreading the routes to reduce the capacitive coupling between nearbywires.

In some embodiments, the NPD detailed routing only explores routes in afinite number of wiring direction, such as nine or more wiringdirections, and does not produce designs with curvilinear routesegments. In some embodiments, the NPD detailed routing is performed byan NPD detailed router that is formed by a topological router and ageometric router, as described above.

After performing the NPD detailed routing at 905, the process 900performs (at 910) PD global routing for the remaining unrouted nets inthe IC design, and after the global routing, performs (at 915) PDdetailed routing for these nets. The purpose of this global routing insome embodiments is to identify routes for nets for which routes werenot identified by the NPD routing at 905 (e.g., nets with nodesseparated by a threshold distance that would not be appropriate forrouting through the first set of wiring layers) or for nets that did nothave complete routes defined by the NPD detailed routing at 905.

The PD detailed routing (at 915) in some embodiments performs pathsearches and identifies route segments (i.e., wire segments) on all theavailable wiring layers (i.e., on the first and second set of wiringlayers) but only along preferred wiring directions that it associateswith each wiring layer. In other embodiments, the PD detailed routing(at 915) performs path searches and identifies route segments (i.e.,wire segments) on the second set of higher PD wiring layers (e.g., thefifth or higher metal layers) and does not explore route segments on thefirst set of lower wiring layers. However, the route segments that thedetailed routing identifies on the second set of wiring layers oftenconnect to route segments that the NPD detailed routing defined on thefirst set of wiring layers.

Like the PD detailed routing (at 915) of some embodiments, the PD globalrouting (at 910) defines global routes that can partially traverse allavailable wiring layers but only along the preferred wiring directionthat the global router associates with each wiring layer. Alternatively,the PD global routing (at 910) in other embodiments defines its globalroutes with respect to the second set of higher wiring layers that onlyhas PD wiring. As mentioned above, in some embodiments the first set ofwiring layers are the first four metal layers of the IC design, and thesecond set of wiring layers are metal layers five and higher of the ICdesign. In other embodiments, the first set of wiring layers justinclude the first two or three metal layers of the IC design, or justinclude the third and/or fourth metal layers.

In some embodiments, the global routing defines global routes traversingmultiple layers as the global routes are defined by reference to athree-dimensional global routing grid. In other embodiments, the globalrouting uses a two-dimensional grid to define two-dimensional globalroutes. In some of these embodiments, the different edges of the globalroute that are along different preferred wiring directions areassociated with the wiring layers that are associated with thosedirections.

In some embodiments, the global and detailed routing operations at 910and 915 use Manhattan preferred directions. Examples of routers thatperform the global and detailed routing operations at 910 and 915include global and detailed routers sold by Cadence, Inc. or Synopsys,Inc. In other embodiments, the global and detailed routing operations at910 and 915 use other preferred direction wiring (e.g., 45 or 60 degreewiring instead of or in conjunction with horizontal and verticaldirection wiring).

FIG. 10 illustrates an NPD detailed routing process 1000 of someembodiments. This process is used (at 905) in some embodiments to defineNPD routes on a set of one or more NPD wiring layers. As shown, thisprocess initially divides (at 1005) the IC design into severalpartitions. FIG. 11 illustrates an example of a portion 1100 of an ICdesign that is partitioned into nine partitions. Next, for eachidentified partition, the process calls (at 1010) an instance of an NPDdetailed router to identify NPD topological routes to connect each netwith nodes that fall in the identified partition.

As mentioned above, the NPD detailed routing of the first set of wiringlayers in some embodiments performs a topological routing operation toidentify topological routes. For each partition that it has to route,the topological NPD detailed router of some embodiments firsttessellates the partition into a plurality of shapes (e.g., polygonssuch as triangles) and then defines the topological routes with respectto the edges of the tessellated shapes. In some embodiments, thetopological router tessellates the partitions into different shapedpolygons than the polygons that are used to divide the IC, e.g., in someembodiments, the partitions are rectangular while the tessellated shapesare triangular. In other embodiments, the tessellated polygons and thepartition polygons have the same shape (e.g., are rectangles) but thetessellated polygons are smaller so that numerous tessellated polygonsare within each partition polygon.

After the topological routes have been defined for each net being routedby the NPD detailed router, the NPD detailed router performs a geometricrouting operation to embed each defined topological route in the ICdesign as a geometric route, as further described below by reference tothe operation 1025 of FIG. 10 .

In some embodiments, the NPD detailed router defines NPD topologicalroutes on multiple wiring layers simultaneously (e.g., on the first fourwiring layers simultaneously). Hence, in these embodiments, the NPDtopological routes that are defined at 1010 can traverse any of thefirst set of wiring layers. As further described below by reference toFIG. 12 , the NPD detailed routing in other embodiments is performed onsuccessive sets of wiring layers (e.g., first on the first wiring layer102 and then on the second wiring layer 104, or first on the first twowiring layers and then on the next two wiring layers when four or morewiring layers are available for NPD wiring in the IC design). In theseembodiments, the NPD topological routes that are defined in eachiteration of a detailed routing through 1010 traverse the set of wiringlayers that are being routed in that iteration of the detailed routing.In addition to these layers, the NPD router in some of these embodimentsalso has at its disposal in each of its iteration the lower wiringlayers that were routed in the previous iterations of the NPD detailedrouting operations.

When the net has nodes that fall in multiple partitions, the topologicalrouting of the NPD detailed router that defines the topological routesfor each partition in some embodiments will identify an NPD topologicalroute that traverses to the partitions boundary so that this NPD routecan later be connected (i.e., stitched) to one or more NPD routes thatare defined in one or more other partitions to connect to the net’snode(s) in the other partition(s). This stitching in some embodiments isperformed (1) by the NPD detailed routing for the next set of NPD wiringlayers when multiple rounds of NPD detailed routing are performed formultiple successive sets of NPD wiring layers, (2) by the PD globaland/or detailed routing that is performed after the NPD detailedrouting, and/or (3) by a post-processing operation of the NPD detailedrouter of some embodiments.

After 1010, the process determines (at 1015) whether it should repeatits detailed topological routing operations for the identifiedpartitions in order to improve its identified NPD topological routes ineach partition and/or to resolve inconsistent partition boundarycrossings that were identified by two or more NPD router instances fortwo or more partitions that contains nodes of the same net. In someembodiments, the NPD topological routing for each partition is intendedto connect the nodes of each net that falls within the partition as muchas possible with the NPD topological routes that are defined byreference to edges that tesselate the NPD wiring layers being routed. Insome embodiments, these edges include the partition edges that definethe partitions (e.g., the nine partitions of FIG. 11 ) on the NPD wiringlayers. These edges in some embodiments also include edges thattessellate the interior of each partition.

In some embodiments, the topological routes are also defined byreference to nodes defined in the tessellated polygons (called faces)that are defined by the edges in each tessellated partition, as thesenodes are used to represent vias to other NPD wiring layers that arebeing concurrently routed by the NPD detailed routing process 1000. Insome embodiments, the topological detailed routing defines eachtopological route in terms of its position to other topological routesalong the tessellated edges and face nodes. In defining these routes,the topological router accounts for the available route capacity alongeach tessellated edge and via capacity along each tessellated face inorder to ensure that too many topological routes are not defined totraverse any location on an NPD wiring layer or any via between tworouted NPD wiring layers.

Due to congestion and other issues, it might not always be possible toconnect the nodes in each partition with just NPD wire segments, or itmight require multiple NPD topological routing iterations to identifyNPD routes to connect all such nodes (e.g., after new constraints aredefined after each iteration). Moreover, two or more NPD routerinstances for two or more partitions that contains nodes of the samenet, initially define routes separately for the nodes that fall withintheir respective partitions. These topological routes might result ininconsistent boundary crossings for the same net. For instance, FIG. 11illustrates two boundary crossings 1112 and 1114 for the same net thatare defined by two different detailed router instances that define NPDroutes for the two neighboring partitions 1105 and 1107. These twoboundary crossings are problematic as they have several othertopological routes (shown with dashed lines) of several other netsbetween them.

When such inconsistent NPD routes exist for multiple partitions thatconnect nodes of one net, or when other non-optimal NPD routes aredefined, the process 1000 in some embodiments determines that it has toperform an additional iteration of its NPD topological routing. As theprocess performs more iterations of its NPD topological routing at 1010,the process 1000 become less likely to perform another iteration of itsNPD detailed routing in some embodiments. For instance, in someembodiments, each inconsistent set of NPD detailed routes or non-optimalNPD detailed routes is allocated a penalty score, and all the penaltyscores are aggregated at 1010 to produce an overall penalty score. Asthe number of iterations through 1010 increases, the process requires ahigher aggregate penalty score to exist before it performs anotheriteration of its NPD detailed routing.

When the process 1000 determines (at 1015) that it has to performanother iteration of its NPD topological routing, the process 1000defines (at 1020) one or more constraints for the next iteration of theNPD topological routing at 1010. Alternatively, for this next iterationof the NPD detailed routing at 1010, the process 1000 shares information(e.g., boundary crossing information) about the different route segmentsthat the different routers identified for the same net among thedifferent partitions, so that the next iteration of topological routingoperations can account for these other routes in defining their next setof routes. After 1020, the process returns to 1010 to perform this nextiteration of routing.

FIG. 12 illustrates an example of a constraint defined at 1020. To avoidthe two inconsistent boundary crossing 1112 and 1114 of the two NPDroutes that are defined for the common net in FIG. 11 , the process 1000in some embodiments defines a constraint that specifies that the NPDdetailed router instances for partitions 1102 and 1104 need to identifytheir respective routes for this net to cross a smaller region 1205 atthis boundary. This smaller region ensures that the two NPD detailedrouter instances would be less likely to identify other NPD routes forother nets in between the two boundary crossings that they identify forthe common net.

Conjunctively or alternatively to defining the constraints at 1020, theprocess 1000 in some embodiments has each particular NPD topologicalrouter instance that routed each particular partition in the previousiteration of 1010 share information about the topological routes that itdefined with (1) each other NPD topological router instance, or (2) eachNPD topological router instance that defined the topological routes forthe partitions that neighbor the particular partition (e.g., for theeight partitions that neighbor the partition 1105 in FIG. 11 ).

In some embodiments, the information provided by each particular NPDtopological router instance to another NPD topological router instanceincludes the entire definition of each topological route defined by theparticular router instance, while in other embodiments the informationincludes just the partition boundary crossings (if any) of eachtopological route that crosses a shared partition boundary. Each NPDtopological router instance then uses the information provided by theother NPD topological router instances in its next iteration through1010. The router instance uses this information to define how thetopological routes that the router instance defines in its nexttopological routing iteration to more closely match the probablelocation of the related topological routes defined by the otherinstances (i.e., the probable location of the other topological routesin the other partitions that have to be stitched to the topologicalroutes being defined by the router instance in its next iteration).

When the process 1000 determines (at 1015) that it does not have toperform another iteration of its NPD detailed routing, the NPD detailedrouting process 1000 uses (at 1025) a geometric detailed router to embedeach defined topological route in the IC design as a geometric route.For each topological route, this embedding defines one or more geometricroute segments along one or more allowable wiring directions, which insome embodiments can include one or more Manhattan and diagonal wiringdirections as well as curvilinear wiring directions that are allowed onan NPD wiring layer. In some embodiments, this geometrization snaps eachtopological route to one or more grid locations along one or moreallowed rectilinear, diagonal and curvilinear directions. After 1025,the process ends.

FIG. 13 illustrates an example of another approach of some embodimentsfor using route crossing data specified by one detailed router instanceof a neighboring partition. In this approach, the IC design partitionsare divided into two groups, a grey group and a white group, that arearranged in a checkerboard fashion. Several detailed router instancesperform NPD detailed routing for the grey partitions first. Thepartition boundary crossings that these routers identify are then passedto the NPD detailed router instances that detailed route the whitepartitions next, so that the NPD routes traversing the white partitionscan respect the boundary crossings identified by the detailed routers ofthe grey partitions. When multiple iterations are performed for thewhite and grey partitions, the router instances for each set of coloredpartitions iteratively pass their boundary crossing information to therouter instances of the next set of colored partitions until the routingiterations end.

FIG. 14 illustrates another NPD detailed routing process 1400 of someembodiments. This process 1400 is similar to the process 1000 exceptthat it iteratively performed NPD detailed routing for different sets ofone or more NPD wiring layers. To that end, the process 1400 hasoperations 1405 and 1410 to select successive sets of one or more NPDwiring layers for detailed routing. After selecting (at 1405) successivesets of NPD wiring layers, the process 1400 in some embodimentsiteratively performs the operations 1010-1020 to identify NPD routesthat traverse the selected sets of NPD wiring layers. When identifyingNPD routes on the currently selected set of NPD wiring layers, theprocess 1400 in some embodiments also explores path search options inone or more lower wiring layers that are part of one or more previouslyselected set of NPD wiring layers. In other embodiments, the process1400 does not explore previously explored lower wiring layers whileidentifying NPD routes on the currently selected set of NPD wiringlayers.

At 1410, the process determines whether it has selected the last set ofNPD wiring layers. If not, the process returns to 1405 to select thenext set of NPD wiring layers and then repeats its operations until itdetermines in its last iteration through 1410 that it has selected thelast set of NPD wiring layers. In some embodiments, the selected set ofNPD wiring layers only includes one wiring layer at a time. In theseembodiments, the process 1400 successively defines NPD routes forsuccessive individual NPD wiring layers, e.g., first for the first NPDwiring layer, then for the second NPD wiring layer, then for the thirdNPD wiring layer, and so on. In other embodiments, the selected set ofNPD wiring layers include two or more NPD wiring layers that areconcurrently selected at 1405 for detailed routing.

Also, in some embodiments, the process 1400 first selects the thirdwiring layer as its first NPD wiring layer to route, and only exploresthe first and second wiring layers for connecting to pins on thesubstrate and for opportunistic path expansions when not finding betteroptions on the third layer. In some of these embodiments, the process1400 uses the first to third wiring layers for the same reasons whileidentifying NPD routes for the fourth NPD wiring layer.

When more than one NPD wiring layer is being routed concurrently withanother NPD wiring layer, the NPD routes that are defined by thedetailed router (that routes the multiple NPD wiring layersconcurrently) can traverse the multiple NPD wiring layers. To traversethe different NPD wiring layers, an NPD route would use vias to connectdifferent segments of the route on different NPD wiring layers.

Some embodiments use multibeam mask writing to enable curvilinear masks,which can then be used to produce curvilinear components on targetwafers and dies. To take advantage of such mask writing and waferproduction, some embodiments provide physical design EDA tools thatproduce curvilinear designs. One example of such physical design toolsare the NPD detailed routers described above that produce curvilinearroutes.

To facilitate the creation of their curvilinear designs (e.g., theircurvilinear routes), the physical design EDA tools of some embodimentsdefine their designs in the pixel domain rather than contour domain.Pixel based designs are also ideal for analyzing and producingcurvilinear designs by using machine learning, because machine learningprocesses are often optimized to process pixel-based data sets. In fact,many machine learning applications do not process contour baseddescriptions of the data sets. Hence, by transforming the physicaldesign (e.g., routing) to operate in the pixel domain instead of thecontour domain, some embodiments make machine learning much moreaccessible for use by the physical design tools.

Similarly, to facilitate the creation of their masks, some embodimentsuse the pixel domain for performing the processing needed to generatetheir masks, because curvilinear masks manipulated in the pixel domaintake the same amount of time as any Manhattan design. Also, thisprocessing is often performed on GPUs in the pixel domain. The vastpower of GPU processing power for this type of pixel manipulations isideal because GPUs are single-instruction multiple-data (SIMD) machinesthat excel in the pixel domain, as a single instruction stream can beapplied to a large number of pixels uniformly. The SIMD architecture canbe relied upon to produce a much higher computing throughput forprocessing physical designs and masks with curvilinear shapes.

Contours (also called geometries) are usually expressed as piecewiselinear polygons, but sometimes expressed with infinite-resolutioncurvilinear formats like splines. Manipulating contours is amathematical dual of manipulating pixel based data, given a resolutionlimit. A mathematical dual means that, functionally, anything that canbe done in one can be done in the other. However, when runtimeperformance or efficiency is taken into account, given a particularaccuracy of result as the target, the computational behavior of one canbe quite different from the other.

In general, manipulating shapes that are mostly large rectangles wouldbe fast in contour domain (i.e., geometry domain), while manipulatingshapes that are largely polygonal or curvilinear with higher vertexdensity would be faster in the pixel domain. In the pixel domain, pixelsize is defined naturally from the resolution limit. Once pixel size isdefined, it does not matter whether the shapes being processed arecurvilinear or rectilinear. The computation either way is constant time.In contour based manipulation, this is not the case as computation timedepends on number of edge count of the piecewise linear that are used torepresent the contours. Also, given that much of the data processingthese data is performed by high powered GPUs, pixel-based analysis ispreferable to contour-based analysis as GPUs are SIMD machines thatexcel in the pixel domain.

To elaborate on these points further, a brief review of IC design andmanufacturing would be helpful. In the past, EDA systems both for designand manufacturing have used Manhattan shapes, often augmented with 45degree edges as the basic building blocks on which to compute. Manhattanshapes are shapes that have axis-parallel edges with 90 degree corners.The fundamental limit in manufacturing semiconductors with shapes otherthan Manhattan shapes had in the past been that all precision layers onthe masks had their masks written with Variable Shaped Beam (VSB) maskwriters that exposed rectangles of certain minimum (e.g., 1 nm-100 nm ona side) sizes and maximum sizes (e.g., 200-1000 nm on a side).

Since VSB writers expose the mask one rectangle at a time, the writetime of a mask is approximately proportional to the number of rectanglesthat need to be written. Diagonals or curves can be approximated with aseries of stair-stepping rectangles. But the number of rectangles wouldbe prohibitively large, making the mask writing time prohibitively longin order to get the approximation to be accurate enough. Even includingthe effects of optical proximity correction (OPC) or the advanced formof OPC called inverse lithography technology (ILT), in order to targetnon-Manhattan shapes on wafer, non-Manhattan shapes on mask becomesnecessary.

Since non-Manhattan shapes on mask, other than for very limited use,were unpractical for VSB writers, non-Manhattan shapes were unviable forsemiconductor design shapes that are the wafer targets. Forty fivedegree triangles are an exception to the Manhattan restriction on VSBmachines. This gave rise to the X-Architecture of Cadence, Inc. Thisarchitecture used 45-degree routing to reduce power consumption and toimprove chip performance.

VSB data preparation techniques using overlapping shots and mask-waferco-optimization are techniques that can be used to target effectivelycurvilinear shapes on mask using reasonable VSB shot counts. But suchtechniques are limited for practical use to 193 i lithography. EUV(extreme ultraviolet) masks have larger numbers of smaller shapes thatneed to be written with more precision (because EUV can “see” betterthan 193 i), so these techniques are not practically viable. Hence, withVSB mask writing, there is no general solution that enables curvilineartarget designs on the wafer.

In the recent years, multibeam mask writers have become available forproduction use in leading mask shops around the world. Multibeam maskwriters write the masks with an array of fixed sized pixels exposing themask. Because the pixel sizes are fixed, the write time of the machinedoes not scale with design complexity or shapes like VSB machines do.This has enabled curvilinear masks to be practically written, just aswell as Manhattan shapes. And this in turn has enabled curvilineartarget design shapes on wafer.

Physical design of semiconductor chips are computer-aided either ininteractive manipulation of geometries or in automatic placement androuting of designs. Either way, physical verification of designs againstphysical rules (such as spacing and minimum width or area rules), aswell as connectivity extraction, and parasitic extraction of electricalparameters (such as resistances, capacitances and inductances) areperformed on physical designs. An overwhelming majority of thesecapabilities today operate in the contour/geometry domain because it hasbeen better to optimize for largely rectangular designs, in fact,largely Manhattan designs, because VSB mask writers could onlyreasonably write the masks to target those wafer shapes.

In contrast to these prior techniques, some embodiments of the inventionuse multibeam mask writing to enable curvilinear masks and thereforecurvilinear design targets on wafer. To take advantage of such maskwriting and wafer production, some embodiments provide physical designtools that produce curvilinear designs. Just as curvilinear designs takethe same amount of time to write on multibeam machines, curvilinearmasks manipulated in the pixel domain take the same amount of time asany Manhattan design.

Moreover, when the processing is performed on GPUs in the pixel domain,because of the vast power of GPU processing power for that type of pixelmanipulations, where a single instruction stream can be applied to allpixels uniformly, the advantages of the SIMD architecture shines toproduce a much higher computing throughput. Just as curvilinear designswould take a long time to write on VSB machines, curvilinear masksmanipulated in the contour/geometry domain take much longer than atypical Manhattan design. This is because regardless of whether thecontour is expressed as piecewise linear polygons of some reasonablevertex interval or as some version of a spline or a NURBS format, therequired vertex count increases with increased curvature, andcomputational algorithms that are in the contour/geometry domain scalein their runtime based on the vertex count.

Given a particular resolution limit, there is no need to representcurvilinear shapes in the contour/geometry domain. In semiconductormanufacturing of curvilinear shapes, that resolution limit is providedby the fact that these mask are written with multibeam mask writers.Multibeam mask writers have a known pixel size that is used to print themask. The resolution limit dictated by that pixel size is the resolutionlimit that can be used to determine the pixel size necessary tomanipulate any semiconductor design in the pixel domain. This is thelower bound on the smallest pixel size that can possibly be required todrive the required precision achievable in the manufacturing process.

Other criteria, however, may further limit the possible resolution ofthe output shapes and therefore the design shapes. For example, ILT iscomputed with pixel doses. Some ILTs operate in the frequency domain(e.g., TrueMask ILT), but that is also representing the mask with pixeldoses. Whether the resolution of the mask and therefore the wafer islimited by the mask writer’s pixel size or by ILT’s pixel size, or someother pixel size, it is clear that there is a physical limit to theachievable resolution of any semiconductor device. This determines thepixel size at which contour/geometry manipulation is a mathematicaldual. However, runtimes of algorithms operating in pixel domain areconstant regardless of shape, regardless of the amount of curvilinearcontent. Moreover, given GPU acceleration, pixel domain computations aremassively parallelizable, which in turn reduces the overall runtimesignificantly.

FIG. 15 illustrates a process 1500 for manufacturing ICs withcurvilinear routes according to some embodiments of the invention. Asshown, the process starts by defining (at 1505) routes in an IC designthat are defined in a pixel domain, or that are converted to the pixeldomain after a routing stage. When defined in the pixel domain, eachroute is expressed in terms of a set of pixels occupied by the route ina three-dimensional space in which the IC design is defined. The ICdesign has one or more NPD wiring layers and one or more PD wiringlayers in some embodiments, while the IC design only has NPD wiringlayers in other embodiments. One or more routes on each NPD wiring layercan be curvilinear routes, with a curvilinear route being a route thathas one or more curvilinear segments. On each NPD wiring layer, theroutes can also traverse in more than eight rectilinear directions insome embodiments.

During routing (at 1505), the process 1500 in some embodiments usesmachine learning to perform its routing operations. For instance, whengeometrizing topological routes at 1025, the process 1000 in someembodiments uses machine learning to identify different probablemanufactured wires that will be produced on the IC or the IC mask forthe different possible geometrizations of the same topological route ofa net, in order to evaluate the different geometrizations and select oneof them as the geometric route for the net.

In some embodiments, the pixel-based definition of each possiblegeometric route for a net is fed to a machine trained network (e.g.,neural network), which then produces the probable manufactured wiresthat are likely to be produced for the geometric route on an IC or theIC mask used to manufacture the IC. The different probable manufacturedwires for the same net are then compared to one or more criteria (e.g.,to design rule checks or capacitance extraction criteria/modeling) todetermine which of the geometric routes results in the probablemanufactured wire that best matches the criteria or does not violate anyof the criteria.

After defining the routes, the process 1500 then performs (at 1510) acompaction operation that uses machine learning to find an optimalcompaction of the routes. Several examples of such compaction operationsare described in U.S. Pat. Application 17/992,876, which is incorporatedherein by reference. Next, at 1515, the process 1500 uses OPC and ILT togenerate curvilinear shapes for the masks. At 1520, the process thenuses a multi-beam mask producing process to produce the masks formanufacturing the IC. At 1525, the process uses the masks to manufacturean IC. After 1525, the process ends.

In some embodiments, the process 1500 iterates between its operations1505-1515 several times in order to produce an IC design with an optimalset of routes for producing acceptable masks and/or manufacturing ICsthat meet desired performance characteristics. These iterations are notshown in FIG. 15 in order not to obscure the description of the process1500 with unnecessary detail. U.S. Pat. Application 16/949,270 describesiteratively performing physical design and mask manufacturing operationsuntil an IC design with desired characteristics is identified. U.S. Pat.Application 16/949,270 is incorporated herein by reference.

As mentioned above, curvilinear wire segments can be inadvertentlycreated on ICs that are designed to have only Manhattan or 45 degreewiring. This is because Manhattan and diagonal jogs on PD wiring layerscan result in curvilinear jogs on these layers because of manufacturinglimitations, i.e., because manufacturing limitations make it hard toproduce 45 or 90 degree junctions.

However, the existing EDA tools today do not produce IC designs withcurvilinear wiring or NPD all-angle rectilinear wiring on the wiringlayers of the designs. This is because the EDA tools do not produce ICdesigns that are to be manufactured with manufacturing processes (e.g.,mask making processes) that are created to produce curvilinear wires andNPD all-angle rectilinear wiring. FIG. 16 illustrates an example of thefive wiring layers 1602-1610 of an IC design produced by one or morephysical design tools (e.g., one or more routers and/or compactors) ofsome embodiments. The first and second wiring layers 1602 and 1604 areNPD curvilinear layers with Manhattan, diagonal and curvilinear routesegments, while the third, fourth and fifth layers 1606, 1608 and 1610are PD layers with alternating Manhattan PD layers.

The five wiring layers 1602-1610 of the IC design in some embodimentsare then used to define the masks that produce the five wiring layers ofthe IC 100 of FIG. 2 . Like the metal layers illustrated in FIG. 16 ,the physical design tools of some embodiments define similar sets ofmetal layers for the IC designs of the other ICs illustrated in theother figures (e.g., FIGS. 1-7 ) described above. Like theircorresponding ICs, the wiring layers in the IC designs of someembodiments have routes on NPD wiring layers with rectilinear (e.g.,Manhattan or diagonal direction) and curvilinear segments. The routes onthese wiring layers are then used to produce masks that can then be usedto produce ICs with NPD rectilinear and curvilinear wiring.

Even though the first two wiring layers 1602 and 1604 are shown to beNPD curvilinear layers, the IC designs in other embodiments have otherNPD wiring layer architectures as described above. For instance, in someembodiments, the third and fourth wiring layers of the IC design are NPDwiring layers, while the first and second wiring layers have blocks ofPD wiring with regions in between that are free for NPD rectilinear andcurvilinear routing.

FIG. 17 illustrates another example of a metal layer 1700 of an ICdesign that is defined to have curvilinear route segments. This metallayer is the fourth metal layer of the IC design. As shown, the fourthmetal layer 1700 has a preferred vertical wiring direction. This layeralso has a bus 1720 with a set of curvilinear jogs 1725, which allow thebus to be re-positioned on the metal layer to avoid an obstacle 1750 onthis layer. The curvilinear jogs 1725 allow the bus to move to the leftas the bus moves from the bottom side of this layer to its top side.

Curvilinear jogs in the IC design are much more preferable to Manhattanor diagonal jogs in the IC design, as curvilinear jogs will be muchcloser to what will be manufactured on the IC and hence are more usefuldesign constructs to analyze for modeling of the IC components in thedesign (e.g., for capacitance extraction modeling). Curvilinear jogs arealso more preferable as they can be manufactured to take up the lessspace than horizontal or diagonal jogs that are defined in the IC design(i.e., curvilinear jogs can be produced more compactly than Manhattan ordiagonal jogs).

Also, curvilinear wiring in IC designs and ICs has certain advantages torectilinear wiring. For instance, curvilinear wire jogs have lessresistance than Manhattan wire jogs as they offer a smoother path forthe electrical flow. Also, as mentioned above, curvilinear jogs are moreaccurately modeled in the IC designs as they are closer to what will endup being produced in the ICs. Moreover, curvilinear jogs are also morereliably manufacturable than Manhattan or diagonal jogs as they arecloser to what will be manufactured than the Manhattan or diagonal jogs.

Vias can be a source of manufacturing reliability issues for ICs. Assuch, some embodiments use curvilinear, NPD routers that are designed toreduce the number of vias. In some embodiments, this reduction at timescomes at the expense of having longer curvilinear, NPD routes onindividual NPD wiring layers, but this expense is acceptable due to thereliability cost of vias and the relatively small cost of slightlylonger short-net connections. FIGS. 18 and 19 illustrate examples of tworouting processes 1800 and 1900 that define curvilinear, NPD routers ina way that reduces the number of vias. FIG. 19 accomplishes this byrouting one NPD wiring layer at a time, while FIG. 18 does this bycosting vias much more expensively than wire length.

As shown, the process 1800 of FIG. 18 initially identifies (at 1805) asubset of short nets to try to route on the NPD wiring layers of an ICdesign that is being routed. In some embodiments, the IC design is thedesign of an entire IC or a portion of the IC. Some embodiments identify“short” nets by using a heuristic to compute an estimated wire lengthfor each net, sorting the nets based on the computed estimates, and thenselecting a subset of the nets based on the sorted order. Examples ofheuristics for each net in some embodiments includes the size boundingbox for the net (e.g., the area of a rectangle that includes all thepins of the net), length of a Steiner tree that connects the pins of thenet, etc.

Also, based on the sorted order, the process 1800 in some embodimentsselects a particular percentage (e.g., 40% or 50%) of the nets for NPD,curvilinear routing (i.e., selects the particular percentage of netsthat have the shortest estimated wirelength based on the sorted order),while in other embodiments, the process 1800 makes this selection basedon another criteria (e.g., by selecting all the nets that have computed,estimated wirelengths smaller than a threshold estimated wirelength).

At 1810, the process 1800 selects a set of two or more wiring layers toroute. In its first iteration through 1810, the process 1800 in someembodiments selects the first and second wiring layers. In someembodiments, the first and second wiring layers have regions withpredefined PD wiring for connecting the electronic components andcircuits of a predefined circuit block (such as an IP block). In suchembodiments, the NPD router identifies NPD rectilinear and curvilinearroutes in the unused spaces between the regions with PD wiring on theselayers. In performing the path searches to identify such routes on thefirst and second wiring layers in these embodiments, the NPD router doesnot penalize any routing directions. After the NPD routing on one of thefirst two layers, more than a threshold amount (e.g., 90%) of the wiresmight still be along a preferred direction, such that the layer stillappears as a PD wiring layer once routing is completed.

At 1815, the process 1800 performs its NPD routing operation to identifyNPD routes that traverse on the NDP wiring layers selected at 1810 foras many of short nets identified at 1805 for which a route has not yetbe defined. The routing operation at 1815 is biased against using viasbut as mentioned above does not penalize any routing directions in orderto bias the routing against any direction.

To bias against vias, the routing process 1800 in some embodiments usesa much higher cost for vias between the NPD wiring layers of the currentset of layers being routed (i.e., last selected at 1810) than thewirelength cost that expresses the cost associated with the length ofroutes on any one of the NPD wiring layer of the current set of layersbeing routed. Also, the via cost between NPD wiring layers in someembodiments is higher than the via costs that are subsequently usedduring the PD routing at 1830 for vias between PD wiring layers orbetween a NPD wiring layer and a PD wiring layer.

Also, in some embodiments, the cost for vias from between two layers isa multiple of the wirelength cost for planar connections on one or bothof these layers. In some of these embodiments, the cost for vias frombetween two NPD layers is a larger multiple of the wirelength cost forplanar connections on one or both of these layers than the via costbetween two PD layers or an NPD layer and a PD layer. For instance, insome of these embodiments, the via cost between two NPD wiring layersthat is assessed by the NPD routing operations at 1815 is M times thewirelength cost for planar connections on one or both of the two NPDwiring layers, while the via cost between two PD wiring layers, orbetween an NPD wiring layer and a PD wiring layer, that is assessed bythe PD routing operations at 1830 is N times the wirelength cost forplanar connections on one or both of the two NPD wiring layers, where Mis greater than N. In some embodiments, M is multiple times larger thanN, e.g., two or three times larger or more.

This biasing against vias reduces the number of vias that the routingoperation at 1815 will define between the NPD wiring layers of thecurrent set of layers being routed. As mentioned above, this reductionin some embodiments can come at the expense of longer curvilinear, NPDroutes on individual NPD wiring layers, but this expense is acceptabledue to the high reliability cost of vias and the relatively small costof slightly longer short-net connections.

Each route that is identified for each net connects the pins of the netin some embodiments. Each identified route can also be a curvilinearroute that has one or more curvilinear edges, or can be a rectilinearroute that only has rectilinear edges. In some embodiments, the routingoperation at 1815 typically includes multiple iterations, with eachiteration conjunctively routing on multiple processing nodes (e.g.,processing cores of one or more multi-core processors of a computerperforming the routing) for several or all partitioned regions of the ICdesign. When one or more short nets span multiple partitions, partitioncrossing locations for each such short net might have to be identifiedthrough successive iterations of the routing operation at 1815 for thesame NPD wiring layer set, in order to determine where and how to stitchtogether route segments defined in different partitions for one.

Examples for connecting different route segments defined for one net indifferent partitions were provided above by reference to FIGS. 11-14 .Also, as described by reference to these figures, some embodimentsperform the NPD routing at 1815 by first identifying topological routesfor the routed, short nets, and then geometrizing the topological routesidentified for these nets. In other embodiments, the NPD routing at 1815is purely a topological routing operation that identifies topologicalroutes for each net, and that after the completion of the NPD routes forall the short nets (e.g., after 1825), is subsequently followed by ageometrization operation that identifies geometric routes for theidentified topological routes.

After performing the routing operation at 1815 for the currentlyselected set of wiring layers, there may be one or more identified“short” nets for which the process 1800 has not yet identified a route.Hence, at 1820, the process 1800 adds these short nets to the list ofshort nets that need to be routed in the next NPD routing iterationthrough 1815 or in the PD routing operation of 1830. In someembodiments, the process 1800 does not need to add the unrouted shortnets to the unrouted list for the NPD routing, as the process maintainsonly one “Nets to Be Routed” list for all of its iterations through theNPD routing operation 1815.

At 1825, the process 1800 determines whether it has selected all theavailable wiring layers that are available for NPD routing. If not, theprocess returns to 1810 to select another wiring layer set for NPDrouting, and then identifies NPD routes on the newly selected wiringlayer set for the remaining unrouted short nets. In some embodiment, thewiring layers that are available for NPD routing are only a subset ofthe wiring layers, e.g., are only layers 1-4 in some embodiments, and donot include all of the wiring layers, e.g., do not include wiring layers5-7.

In some embodiments, the wiring layer sets selected in successiveiterations for NPD routing through 1810 are not overlapping, while inother embodiments they are different sets but can overlap with one ormore wiring layers in common between two sets selected in two iterationsthrough 1810. Irrespective of whether successive selected sets of wiringlayers overlap, a subsequently selected wiring layer set will include atleast one higher wiring layer that was not in the earlier selectedwiring layer set(s).

In some embodiments, when the process 1800 routes all or most of theshort nets on a previously selected wiring layer set, the process 1800adds to the list of “Nets to be Routed” one or more “medium” or longerlength nets to be routed on the subsequently selected wiring layer set(i.e., the wiring layer set selected at 1810 after last iterationthrough 1825). This approach ensures that NPD routing is used as much aspossible for as many nets as possible. In some embodiments, the process1800 adds the longer nets to the “Nets to be Routed” list based on theirestimated wirelengths (as computed by one of the above-describedheuristics) with the nets with smaller estimated wirelengths addedbefore the nets with the larger estimates.

When the process determines (at 1825) that it selected all the wiringlayer sets that are available for NPD routing, the process then calls(at 1830) a PD router to route the remaining unrouted nets. In some ofthe embodiments in which the routing operation at 1815 is purely atopological routing operation, the process 1800 uses a geometric routerto generate geometric routes for the topological routes defined for oneor more sets of NPD wiring layers at 1815, before calling the PD routerto route the remaining unrouted nets. The PD router in some embodimentstreats the NPD routes defined by the process 1800 as obstacles in therouting graph, but otherwise proceeds with the routing of the unroutednets with PD routes defined on all the wiring layers, including the NPDwiring layers routed by the NPD routing process 1800. After 1830, theprocess ends.

In some embodiments, the NPD routing operations 1805-1825 of the process1800 are performed by an NPD router, while the PD routing operation 1830is performed by a separate PD router. In other embodiments, both the NPDrouting operations and the PD routing operations are performed by onerouter that performs NPD routing on a first set of wiring layers (e.g.,layers one through four), while performing PD routing on a second set ofwiring layers (e.g., layers five and above). To ensure that the NPDrouting is only used for shorter nets, the routing process 1800 in someembodiments penalize NPD routes that are longer than a thresholddistance or place constraints that prevents these routes from beinglonger than a threshold distance.

FIG. 19 illustrates an NPD routing process that reduces the number ofvias between the NPD wiring layers by routing one NPD wiring layer at atime. This reduction can come at the expense of longer curvilinear, NPDroutes on individual wiring layers, but this expense is acceptable dueto the reliability cost of vias and the relatively small cost of longershort-net connections.

As shown, the process 1900 initially identifies (at 1905) a subset ofshort nets to try to NPD route on the wiring layers of an IC design thatis being routed. In some embodiments, the IC design is the design of anentire IC or a portion of the IC. Some embodiments identify “short” netsby using a heuristic to compute an estimated wire length for each net,sorting the nets based on the computed estimates, and then selecting asubset of the nets based on the sorted order. Examples of suchheuristics were provided above by reference to FIG. 18 .

At 1910, the process 1900 selects a particular wiring layer (also calledrouting layer) that is the next lowest wiring layer that is availablefor NPD routing and that the process has not yet selected for NPDrouting. In some embodiments, the process 1900 initially selects (at1910) the first wiring layer, and in its subsequent iterations through1910 steps through the remaining wiring layers that are available forNPD routing, e.g., steps through layers 2-4. In other embodiments, theprocess 1900 initially selects (at 1910) the third wiring layer, and inits subsequent iterations through 1910 steps through the remainingwiring layers that are available for NPD routing, e.g., steps throughlayer 4. In some embodiments, the wiring layers that are available forNPD routing are only a subset of the wiring layers, e.g., are onlylayers 1-4 in some embodiments, and do not include all of the wiringlayers, e.g., do not include wiring layers 5-7.

Next, at 1915, the process 1900 identifies NPD routes that traverses onthe wiring layer selected last at 1910 for as many of short netsidentified at 1905 for which a route has not yet be defined. Each NPDroute that is identified for each net connects two or more nodes (e.g.,two or more pins) of the net in some embodiments. Each identified NPDroute can be a curvilinear route that has one or more curvilinear edges(along with zero or more rectilinear edges), or can be a rectilinearroute that only has rectilinear edges.

To identify each NPD route for each net during each iteration through1915 that is performed for a selected particular wiring layer, theprocess 1900 performs a path search that identifies a path between thetwo or more nodes of the net that are to be connected, and then embedsthe identified path as a route between the two or more nodes. This pathsearch in some embodiments does not explore path expansions to anywiring layer above the particular NPD wiring layer in order to identifya path that traverses to a higher wiring layer and then traverses backto the particular NPD wiring layer or a lower layer. In someembodiments, this path search explores path expansions on the selectedparticular wiring layer and any wiring layers below the selectedparticular wiring layer. In other embodiments, this path search explorespath expansions only on the selected particular wiring layer. In some ofthese embodiments, the path search for a net can identify incompleteroutes for a net that terminate on via locations to higher layers.Subsequent iterations of the NPD or PD routing that are performed forthe higher layers then perform path searches starting from these vialocations to complete the routes for these nets in some embodiments.

These differing path search approaches of different embodiments resultin different routes being defined during the routing operation at 1915for each particular wiring layer selected at 1910. In some embodiments,the routing operation at 1915 for the selected particular wiring layerdoes not use vias to any higher wiring layers that it has not yetselected in any iteration through 1910, in order to identify a routethat traverses to the higher layer and then traverses back down to theselected particular wiring layer or a lower layer. Also, this routingoperation in some embodiments only uses vias to connect the selectedparticular wiring layer to the lower layers (1) on which the pins of thenets (being routed) are defined or (2) on which route segments for thesenets were previously identified in previous iteration(s) through 1910(iterations before the current iteration through 1910).

Other embodiments implement the “No Via” constraint differently. Forinstance, to reduce or eliminate vias to the lower wiring layers duringthe routing of any one particular wiring layer, the routing operationsfor a lower wiring layer that is below the particular wiring layeridentifies via locations for traversing from the lower wiring layer tothe particular wiring layer, as mentioned above. Conjunctively, oralternatively, in some embodiments, the NPD routing process 1900 at thestart of the NPD routing for any one wiring layer (selected at 1910)defines expected contact locations on the selected wiring layer forconnecting to lower layer pins or pin contacts. For any given pin, suchan expected contact location on the selected wiring layer is directlyabove the pin or pin contact when there is no obstacle to the lower pinor pin contact, or is at an offset location over the lower pin or pincontact, where the offset location is connected to the pin or pincontact through wiring defined on the lower substrate and wiring layersthrough route segments defined by the NPD routing process 1900 beforestarting the NPD routing of the selected wiring layer.

In some embodiments, the routing operation at 1915 typically includesmultiple iterations, with each iteration conjunctively routing onmultiple processing nodes (e.g., processing cores of one or moremulti-core processors of a computer performing the routing) allpartitions of the IC design that is being routed by the process 1900.When one or more short nets span multiple partitions that are used todivide the routing region, partition crossing locations are identifiedaccording to one of the manners described above by reference to FIGS.11-14 and 18 .

Also, as described by reference to these figures, some embodimentsperform the NPD routing at 1915 by first identifying topological routesfor the routed, short nets, and then geometrizing these nets. In otherembodiments, the NPD routing at 1915 is purely a topological routingoperation that identifies topological routes for each net, and thatafter the completion of the NPD routes for all the short nets (e.g.,after 1925) is followed by a geometrization operation that identifiesgeometric routes for the topologically identified routes.

After performing 1915 for the currently selected wiring layer (i.e., thewiring layer last selected at 1910), there may be one or more identified“short” nets for which the process 1900 has not yet identified a route.Hence, at 1920, the process 1900 adds these short nets to the list ofshort nets that need to be routed in the next NPD routing iterationthrough 1915 or in the PD routing operation of 1930. In someembodiments, the process 1900 does not need to add the unrouted shortnets to the unrouted list for the NPD routing, as the process maintainsonly one “Nets to Be Routed” list for all of its iterations through theNPD routing operation 1915.

At 1925, the process 1900 determines whether it has selected all thewiring layers that are available for NPD routing. If not, the processreturns to 1910 to select the next higher level wiring layer that isavailable for NPD routing, and then identifies NPD routes on the newlyselected wiring layer for the remaining unrouted short nets.

In some embodiments, when the process 1900 routes all or most of theshort nets on the previously selected NPD wiring layer(s), the process1900 adds to the list of “Nets to be Routed” one or more “medium” orlonger length nets to be routed on the currently selected NPD wiringlayer (i.e., the NPD wiring layer selected at 1910 after last iterationthrough 1925). This approach ensures that NPD routing is used as much aspossible for as many nets as possible. In some embodiments, the process1900 adds the longer nets to the “Nets to be Routed” list based on theirestimated wirelengths (as computed by one of the above-describedheuristics) with the nets with smaller estimated wirelengths addedbefore the nets with the larger estimates.

When the process determines (at 1925) that it selected all the wiringlayers that are available for NPD routing, the process then calls (at1930) a PD router to route the remaining unrouted nets. In someembodiments in which the routes defined at 1915 are topological routes,the process 1900 performs a geometrization operation after 1925 todefine geometric routes for the topological routes, before calling thePD router to route the remaining unrouted nets. The PD router in someembodiments treats the NPD routes defined by the process 1900 asobstacles in the routing graph, but otherwise proceeds with the routingof the unrouted nets with PD routes defined on all the wiring layers,including the wiring layers that were used by the NPD router to defineNPD routes. After 1930, the process ends.

In some embodiments, the NPD routing operations 1905-1925 of the process1900 are performed by an NPD router, while the PD routing operation 1930is performed by a separate PD router. In other embodiments, both the NPDrouting operations and the PD routing operations are performed by onerouter that performs NPD routing on a first set of wiring layers (e.g.,layers one through four), while performing PD routing on a second set ofwiring layers (e.g., layers five and above). To ensure that the NPDrouting is only used for shorter nets, the routing process 1900 in someembodiments penalize NPD routes that are longer than a thresholddistance or place constraints that prevents these routes from beinglonger than a threshold distance.

By not exploring via path expansions, or limiting via path expansions toreach an unrouted net’s pin or pin contact, the NPD routing process 1900drastically reduces the number of vias that it define. This reduction insome embodiments can come at the expense of longer curvilinear, NPDroutes on individual NPD wiring layers, but this expense is acceptabledue to the high reliability cost of vias versus the relatively smallcost of longer short-net connections.

FIGS. 20-22 present an example that illustrates the dramatic decrease inthe number of vias that is gained by using the NPD routing process 1900of FIG. 19 . FIG. 20 illustrates a set of nets that need to be connectedthrough routes. In this figure, the pins 2005 of each net that need tobe connected are linked through one or more rectilinear lines 2010. Eachconnected set of lines and pins effectively represents a net that needsto be connected. As mentioned above, a net in some embodiments is acollection of pins that need to be connected.

FIG. 21 illustrates traditional Manhattan routes on metal layers 3 and 4that connect the pins of each of several nets illustrated in FIG. 20 .In FIG. 21 , the solid lines are on metal layer 3 with preferredhorizontal direction wiring, while the dashed lines are on metal layer 4with preferred vertical direction wiring. Each route in several of thedisplayed routes has one or more horizontal route segments that aredefined on horizontal PD metal layer 3 and that are connected to one ormore vertical route segments defined on vertical PD metal layer 4. Ineach such route, each pair of connected horizontal and vertical segmentpairs is connected through a vias, which results a very large number(e.g., 176) of vias in FIG. 21 .

FIG. 22 illustrates the curvilinear, NPD routes on metal layers 3 and 4that connect the pins of each of several nets illustrated in FIG. 20 .In FIG. 22 , the solid lines are on metal layer 3 with NPD directionwiring, while the dashed lines are on metal layer 4 with NPD directionwiring. Each NPD route has one or more curvilinear route segments thatare defined on one or two curvilinear NPD wiring layers. In each suchroute, the NPD route only uses vias to get to the NPD wiring layer onwhich the route is defined from the pins connected to the route, anddoes not use a via to connect a solid route segment on layer 3 with adashed route segment on layer 4. This approach results in a dramaticallysmaller number (e.g., 20) of vias in FIG. 22 . This approach comes atthe expense of some of the NPD routes on a given NPD layer havingslightly longer lengths, especially when going around obstacles on anNPD layer. Examples of such longer length NPD routes (that are longer togo around obstacles) include NPD routes 2220, 2222, and 2224.

Also, in the example of FIG. 22 , most of the NPD routes are defined onthe third metal layer (i.e., most of the routes are in displayed withsolid lines). This is because tolerating longer curvilinear wires on oneNPD wiring layer while avoiding vias to the other NPD wiring layer,allows most of the routes to be defined on just one NPD wiring layer.The longer length of the curvilinear routes on metal layer 3 can betolerated as these routes are still relatively short (i.e., do notrequire buffering) and avoid vias, which are sub-optimal from amanufacturing point of view. This approach also consumes less area onmetal layer 4, which now can be used to define NPD wiring for some ofthe medium sized nets.

FIG. 23 illustrates an NPD router 2300 of some embodiments. As shown,the NPD router 2300 includes a topological router 2305, a geometricrouter 2310 and a post-routing optimizer 2315. The topological router2305 in some embodiments tessellates each NPD wiring layer or apartition of each such layer of the IC design into several polygons(also called faces), and then defines topological routes (to connectnets) by reference to the edges of the tessellated layers.

A particular topological route has its position defined in terms of itsrelative position with respect to other topological routes along theedges crossed by the particular topological route. Some embodiments alsouse nodes associated with faces of the polygons to model vias betweenNPD wiring layers traversed by topological routes. In these embodiments,the topological routes are defined by not only the edge but also theface nodes and their relative position with respect to each other byreference to these edges and face nodes. In some embodiments, eachparticular topological route is also defined by the coordinates of apair of nodes (of the netlist) connected by the topological route, orjust by reference to the pair of nodes as the starting and ending pointof the topological route.

The geometric router 2310 in some embodiments defines a geometricrealization for each topological route defined by the topological router2305. In some embodiments, the geometric router snaps each topologicalroute to a grid (imposed on the wiring layers) along the allowed wiringdirections for the layer. In the embodiments that allow curvilinearsegments, this snapping allows for wire segments to be curvilinear. Togenerate the geometric realization of a topological route, the geometricrouter 2310 in some embodiments explores rectilinear and curvilinearrealization of edges in the topological route and thereby producesrectilinear and curvilinear edges.

In some embodiments, the geometric router 2310 specifies specificspacing between the routes as it defines specific geometric coordinatesfor the geometric routes that it defines, while the topological router2305 does not specify specific geometric coordinates for the topologicalroutes that it defines. However, in some embodiments, the topologicalrouter accounts for expected wire thickness of the topological routes inorder to keep track of congestion along the tessellated edges.

The post-routing optimizer 2315 tries to improve the geometric routesproduced by the geometric router 2310 based on one or more optimizationcriteria. In improving a geometric route, the post-routing optimizer insome embodiments can move one or more edges of the geometric route,and/or further define the geometric route by providing additional edgesin the geometric route or combining some edges in the geometric route.

In some embodiments, the optimizer 2315 is a compactor that defines amore tight compaction of the geometric route. The optimization criteriain this instance reducing the size of the IC design. In otherembodiments, the optimization criteria includes timing criteria orspacing criteria that directs the optimizer 2315 to more evenly spacethe geometric routes produced by the geometric router 2310 to improvethe timing performance of the signals traversing interconnect that isproduced based on these routes.

A more even distribution of the geometric routes will lead to areduction in parasitic capacitance due to proximity of interconnectlines that are produced based on the geometric routes. In other words,more evenly spacing the routes reduce the parasitic capacitive load onthe wires, which in turn, reduces signal delay due to parasiticcapacitance. In still other embodiments, the post-routing optimizer 2315tries to modify the geometric routes based on other criterion and/orbased on multiple criteria.

As shown, the NPD router 2300 has a feedback loop from the post-routingoptimizer 2315 to the geometric router 2310. The optimizer 2315 usesthis feedback loop when it directs the geometric router 2310 to identifya better set of one or more geometric routers for one or more nets inthe IC design or partition being routed when the optimizer determinesthat this set of routes has sub-optimal performance (e.g., has too muchcapacitive load, or is too long to meet timing constraints). Thepost-routing optimizer 2315 in some embodiments can direct the geometricrouter 2310 to identify better sets of routes in multiple iterationsuntil the optimal set of geometric routes are identified for a set ofnets.

In some embodiments, the geometric router 2310 only defines an initialgeometric route for each topological route, and leaves the finaldefinition of the geometric route for post-routing optimizer 2315, whichthen defines the specific geometric routes based on one or morecriteria, such as compacting the design to reduce the overall die size,or spreading the routes to reduce the capacitive coupling between nearbywires. For instance, in some embodiments, a topological route does nothave any width or specific coordinates for its segments, other than thecoordinates of the two nodes (e.g., two pins) connected by thetopological route.

Instead of snapping each topological route to a grid, the geometricrouter in some embodiments defines a width for each topological route,and then leaves it to a subsequent compactor to geometrize fully theroute (e.g., to produce a full geometric definition of the route). Insome such embodiments, the geometric router defines for each topologicalroute some intermediate coordinates for the route so that the geometricroute that it produces for the topological route not only has some widthbut also has one or more intermediate coordinates that define two ormore route segments. Based on a set of one or more criteria, thepost-routing optimizer 2315 then defines the specific geometric routes.In some embodiments, the post-routing optimizer 2315 comprises acompactor that uses a machine-trained network to improve geometricroutes produced by the geometric router. The above-incorporated US Pat.Application 17/992,876 describes several examples of compactors that usemachine-trained network to improve routes in IC designs.

FIG. 24 illustrates an NPD router 2400 of some embodiments that has ageometric router 2410 with a machine learning engine (e.g., amachine-trained neural network) that identifies geometric routes for aset of nets for which a topological router 2405 of the NPD router 2400identifies topological routes. This figure shows the topological router2405 providing a set of topological routes 2402 that it identifies for aset of nets on an NPD wiring layer. Each topological route is defined byreference to edges 2404 of rectangular grid cells 2406 that tessellate apartition of an NPD wiring layer. In this example, four grid cells 2406are shown that include four topological routes 2402 two of which goaround an obstacle 2408 in one of the cells. When more than onetopological route crosses an edge, each topological route’s crossing ofthat edge is defined with respect to where any other topological routecrosses that same edge, e.g., one route’s edge crossing is identified asbeing between one vertex of the edge and another route’s edge crossing.

FIG. 24 also shows the geometric router 2410 produces four geometricroutes 2412 for the four topological routes 2402. In some embodiments,each geometric route is defined by specific geometric coordinatesassociated with the pixels that define each geometric route. In someembodiments, the geometric router 2410 uses a machine-trained neuralnetwork that as input takes the topological routes (e.g., the edgecrossings of each topological route) and produces as output thegeometric routes corresponding to the input topological routes. Also, insome embodiments, the geometric routes produced by the geometric routerare routes that mimic the expected manufactured shapes of the routes.

In some embodiments, the neurons of the neural network are trained byusing numerous previously computed training sets with each set includinga pair of input topological routes and their corresponding outputgeometric routes that were computed by a geometric router that used oneof the known EDA techniques to geometrize the topological routes (e.g.,by snapping the topological routes to a grid). The output geometricroutes in some embodiments are the manufactured shapes of the geometricroutes, which in some embodiments are produced by examining actualinterconnect shapes after the manufacturing, while in other embodimentsare produced by passing each training set geometric route through amachine-trained network that produces expected manufactured shape of thegeometric route. Several of the training sets also include obstaclesthat are defined in the region traversed by the topological andgeometric routes.

During training, the topological route of each training pair is fedthrough the neural network to produce an output geometric route, whichis then compared to the training pair’s geometric route to produce adifference value. The difference values for several training pairs arethen used to compute a loss function value, which is then backpropagated through the neural network to reconfigure the trainableparameters of the neural network.

In some embodiments, multiple instances of the NPD router concurrentlydefine routes for multiple partitions of one NPD wiring layer of an ICdesign. For instance, in some of these embodiments, each instance of thetopological router (that defines topological routes for one partition)of the NPD router tessellates its partition into several (e.g., 16, 32,50, 100, 128, 256) rectangular cells, and then defines its topologicalroutes by reference to the edges of these cells that are crossed by thetopological routes. To geometrize each of the topological routesidentified by its topological router instance, the geometric routerinstance in some of these embodiments iteratively (1) selects differentsets of neighboring rectangular cells and (2) uses its machine-trainedneural network to geometrize the portion of the topological routes thatpass through the selected sets of neighboring rectangular cells.

For instance, FIG. 25 illustrates an example when the topological router2405 tessellates a partition into 64 rectangular cells 2502, which itthen uses to define topological routes. This figure also shows thegeometric router 2410 in some embodiments using its machine-trainedneural network four times to geometrize the topological routes passingfirst through the top-left sixteen cells 2512, the top-right sixteencells 2514, the bottom-left sixteen cells 2516 and the bottom-rightsixteen cells 2518. In some embodiments, the topological router 2405tessellates the partition that it is routing into many more cells than64.

Some embodiments concurrently execute multiple instances of the NPDrouter on multiple processing cores of a computer, in order to defineroutes for multiple partitions of one NPD wiring layer or a set of twoor more NPD wiring layers of an IC design. This approach allows the datacomputed for each partition by each NPD router instance to be sharedwith another NPD router instance, which needs access to this data whenperforming multiple iterations of its routing operations that rely upondata computed by other NPD router instances. The NPD router instancescan share data through messaging or through a common memory that theyshare.

For instance, for an Nth iteration of its routing operation, a first NPDrouter instance that defines the topological routes for a first cellneeds to know about the topological routes computed by a second NPDrouter instances that defines the topological routes for a second cellthat neighbors the first cell, when the first and second NPD routerinstances respectively compute first and second route segments of atleast one net’s topological route that traverses the first and secondcells.

In such a case, the first NPD router instance would need to know aboutwhere the second topological route segment (computed for a particularnet by the second NPD router instance) crosses a shared edge between thefirst and second cells. This knowledge allows the first NPD routerinstance to ensure that it does not define a conflicting edge-crossinglocation for the first topological route segment that it computes acrossthe same edge for the particular net. It should be noted that typicallyshort nets will fall in one or two neighboring partitions, which resultsin their routes traversing only one to three partitions, with the caseof three partitions typically involving a net that has pins in twodiagonally adjacent partitions for which the route would need totraverse to another horizontally/vertically adjacent partition to reachthe neighboring diagonal partition.

In some embodiments, the size of the partitions used to divide an NPDwiring layer or a set of two or more NPD wiring layers that areconcurrently routed by an NPD router, is related to the amount ofcompute and memory resources of a computer that is used to performconcurrent NPD routing of some or all of the partitions. FIGS. 26 and 27illustrate two alternative processes 2600 and 2700 for defining apartition size that is related to the amount of compute and memoryresources of a computer. In these examples, multiple NPD routersconcurrently define NPD routes (e.g., topological NPD routes) for someor all of the partitions that are used to divide one NPD wiring layer,or a set of two or more NPD wiring layers, that is being routed.

The process 2600 of FIG. 26 first selects (at 2605) the desiredpartition size to divide the routing region (e.g., an NPD wiring layerof an IC design) into multiple partitions that will be concurrentlyrouted on multiple processing cores of a computer. The process 2600 thenselects a computer that has sufficient amount of compute and memoryresources (e.g., the number of cores and the amount of cache or RAMmemory) to concurrently process the NPD routing (e.g., the topologicalrouting) of all the partitions on the multiple NPD router instances thatconcurrently run and share their data in a common memory.

In some embodiments, the NPD router instances do not share memory butcommunicate data regarding their respective routing of neighboringpartitions through messaging or some other mechanism. Also, in someembodiments, each NPD router instance is allocated enough memory toallow the data that the router instance computes in each iteration ofits routing for a partition to remain in memory (as opposed to movingthe data first to disk and then back to memory) for the router instanceto use in its next iteration of its routing operation.

The process 270 of FIG. 27 , on the other hand, first selects (at 2705)the computer that will execute the multiple NPD router instances thatconcurrently execute to route some or all of the partitions of therouting region (e.g., an NPD wiring layer of an IC design). Thiscomputer has a particular amount of compute and memory resources (e.g.,a particular number of cores and amount of cache or RAM memory), basedon which the process 2700 then specifies the desired partition size todivide the routing region into several partitions that will beconcurrently routed on the multiple processing cores of the computer.

Many of the above-described features and applications are implemented assoftware processes that are specified as a set of instructions recordedon a computer readable storage medium (also referred to as computerreadable medium). When these instructions are executed by one or moreprocessing unit(s) (e.g., one or more processors, cores of processors,or other processing units), they cause the processing unit(s) to performthe actions indicated in the instructions. Examples of computer readablemedia include, but are not limited to, CD-ROMs, flash drives, RAM chips,hard drives, EPROMs, etc. The computer readable media does not includecarrier waves and electronic signals passing wirelessly or over wireconnections.

In this specification, the term “software” is meant to include firmwareresiding in read-only memory or applications stored in magnetic storage,which can be read into memory for processing by a processor. Also, insome embodiments, multiple software inventions can be implemented assub-parts of a larger program while remaining distinct softwareinventions. In some embodiments, multiple software inventions can alsobe implemented as separate programs. Finally, any combination ofseparate programs that together implement a software invention describedhere is within the scope of the invention. In some embodiments, thesoftware programs, when installed to operate on one or more electronicsystems, define one or more specific machine implementations thatexecute and perform the operations of the software programs.

FIG. 28 conceptually illustrates an electronic system 2800 with whichsome embodiments of the invention are implemented. The electronic system2800 may be a computer (e.g., a desktop computer, personal computer,tablet computer, server computer, mainframe, a blade computer etc.), orany other sort of electronic device. As shown, the electronic systemincludes various types of computer readable media and interfaces forvarious other types of computer readable media. Specifically, theelectronic system 2800 includes a bus 2805, processing unit(s) 2810, asystem memory 2825, a read-only memory 2830, a permanent storage device2835, input devices 2840, and output devices 2845.

The bus 2805 collectively represents all system, peripheral, and chipsetbuses that communicatively connect the numerous internal devices of theelectronic system 2800. For instance, the bus 2805 communicativelyconnects the processing unit(s) 2810 with the read-only memory (ROM)2830, the system memory 2825, and the permanent storage device 2835.From these various memory units, the processing unit(s) 2810 retrieveinstructions to execute and data to process in order to execute theprocesses of the invention. The processing unit(s) may be a singleprocessor or a multi-core processor in different embodiments.

The ROM 2830 stores static data and instructions that are needed by theprocessing unit(s) 2810 and other modules of the electronic system. Thepermanent storage device 2835, on the other hand, is a read-and-writememory device. This device is a non-volatile memory unit that storesinstructions and data even when the electronic system 2800 is off. Someembodiments of the invention use a mass-storage device (such as amagnetic or optical disk and its corresponding disk drive) as thepermanent storage device 2835.

Other embodiments use a removable storage device (such as a floppy disk,flash drive, etc.) as the permanent storage device. Like the permanentstorage device 2835, the system memory 2825 is a read-and-write memorydevice. However, unlike storage device 2835, the system memory is avolatile read-and-write memory, such a random access memory. The systemmemory stores some of the instructions and data that the processor needsat runtime. In some embodiments, the invention’s processes are stored inthe system memory 2825, the permanent storage device 2835, and/or theread-only memory 2830. From these various memory units, the processingunit(s) 2810 retrieve instructions to execute and data to process inorder to execute the processes of some embodiments.

The bus 2805 also connects to the input and output devices 2840 and2845. The input devices enable the user to communicate information andselect commands to the electronic system. The input devices 2840 includealphanumeric keyboards and pointing devices (also called “cursor controldevices”). The output devices 2845 display images generated by theelectronic system. The output devices include printers and displaydevices, such as cathode ray tubes (CRT) or liquid crystal displays(LCD). Some embodiments include devices such as a touchscreen thatfunction as both input and output devices.

Finally, as shown in FIG. 28 , bus 2805 also couples electronic system2800 to a network 2865 through a network adapter (not shown). In thismanner, the computer can be a part of a network of computers (such as alocal area network (“LAN”), a wide area network (“WAN”), or an Intranet,or a network of networks, such as the Internet. Any or all components ofelectronic system 2800 may be used in conjunction with the invention.

Some embodiments include electronic components, such as microprocessors,storage and memory that store computer program instructions in amachine-readable or computer-readable medium (alternatively referred toas computer-readable storage media, machine-readable media, ormachine-readable storage media). Some examples of such computer-readablemedia include RAM, ROM, read-only compact discs (CD-ROM), recordablecompact discs (CD-R), rewritable compact discs (CD-RW), read-onlydigital versatile discs (e.g., DVD-ROM, dual-layer DVD-ROM), a varietyof recordable/rewritable DVDs (e.g., DVD-RAM, DVD-RW, DVD+RW, etc.),flash memory (e.g., SD cards, mini-SD cards, micro-SD cards, etc.),magnetic and/or solid state hard drives, read-only and recordableBlu-Ray® discs, ultra density optical discs, any other optical ormagnetic media, and floppy disks. The computer-readable media may storea computer program that is executable by at least one processing unitand includes sets of instructions for performing various operations.Examples of computer programs or computer code include machine code,such as is produced by a compiler, and files including higher-level codethat are executed by a computer, an electronic component, or amicroprocessor using an interpreter.

While the above discussion primarily refers to microprocessor ormulti-core processors that execute software, some embodiments areperformed by one or more integrated circuits, such as applicationspecific integrated circuits (ASICs) or field programmable gate arrays(FPGAs). In some embodiments, such integrated circuits executeinstructions that are stored on the circuit itself.

As used in this specification, the terms “computer”, “server”,“processor”, and “memory” all refer to electronic or other technologicaldevices. These terms exclude people or groups of people. For thepurposes of the specification, the terms display or displaying meansdisplaying on an electronic device. As used in this specification, theterms “computer readable medium,” “computer readable media,” and“machine readable medium” are entirely restricted to tangible, physicalobjects that store information in a form that is readable by a computer.These terms exclude any wireless signals, wired download signals, andany other ephemeral or transitory signals.

While the invention has been described with reference to numerousspecific details, one of ordinary skill in the art will recognize thatthe invention can be embodied in other specific forms without departingfrom the spirit of the invention. For instance, a number of the figuresconceptually illustrate processes. The specific operations of theseprocesses may not be performed in the exact order shown and described.The specific operations may not be performed in one continuous series ofoperations, and different specific operations may be performed indifferent embodiments. Furthermore, the process could be implementedusing several sub-processes, or as part of a larger macro process.Therefore, one of ordinary skill in the art would understand that theinvention is not to be limited by the foregoing illustrative details,but rather is to be defined by the appended claims.

1. A method of performing curvilinear routing for an integrated circuit design, the method comprising: performing a topological routing operation to identify a plurality of topological routes for a plurality of nets; and performing a geometric routing operation to identify a plurality of geometric routes for the identified plurality of topological routes, said identified geometric routes comprising a plurality of curvilinear routes with curvilinear segments.
 2. The method of claim 1, wherein each topological route in a set of topological routes has a plurality of possible geometric routes that are possible geometric realizations of the topological route.
 3. The method of claim 1, wherein each of a plurality of topological route has positional information defined by reference to at least one other topological route, while each geometric route is defined by reference to specific coordinates that define one or more route segments of the geometric route.
 4. The method of claim 1, wherein each topological route also has positional information defined by references to at least two nodes in the IC design connected by the topological route.
 5. The method of claim 3, wherein performing the topological routing operations comprises tessellating one or more routing layers into a plurality of polygons and defining the topological routes by reference to edges of the polygons.
 6. The method of claim 5, wherein the geometric routing operation specifies spacing between the geometric routes, while the topological routing operation does not specify specific spacing as the topological routing operation does not define geometric coordinates for the entirety of each topological route.
 7. The method of claim 5, wherein the geometric routing operation specifies spacing between the geometric routes, while the topological routing operation does not specify specific spacing as the topological routing operation does not define geometric coordinates for each end of each segment of each topological route that the topological routing operation defines.
 8. The method of claim 7, wherein the topological routing operation accounts for expected wire thickness of the topological routes in order to keep track of congestion along the polygon edges.
 9. The method of claim 1 further comprising performing a post-processing operation to optimize one or more identified geometric routes based on one or more optimization criteria.
 10. The method of claim 9, wherein the geometric routing defines geometric routes by defining widths for the identified topological routes, and the post-processing operation modifies the geometric routes based on the optimization criteria.
 11. The method of claim 10, wherein the optimization criteria comprises a spacing criteria to spread out the geometric routes in order to reduce capacitive coupling between the geometric routes.
 12. The method of claim 10, wherein the optimization criteria comprises a compaction criteria to pack the geometric routes in order to reduce size of an IC die on which the IC is manufactured.
 13. The method of claim 9, wherein the optimization criteria comprises user selectable criteria that a user selects in order to improve the performance of the IC design.
 14. The method of claim 13, wherein the user-selectable optimization criteria further comprising reducing the area consumed by the geometric routes; wherein the performing of the post-processing operation comprises directing a compactor to compact the geometric routes when a user selects area reduction as the optimization criteria.
 15. The method of claim 13 further comprising modifying at least a subset of the geometric routes to be further away from at least some of their neighboring routes when the user selects spacing out the geometric routes to improve timing performance of signals traversing wires that will be produced based on these routes.
 16. The method of claim 9, wherein the post-processing optimizes the geometric routes by directing a geometric router that performed the geometric routing operation to re-perform a routing operation for a subset of nets.
 17. The method of claim 9, wherein the post-processing optimizes the geometric routes without directing a geometric router that performed the geometric routing operation to re-perform any routing operation for any subset of nets.
 18. The method of claim 9, wherein the post-processing operation modifies one or more geometric routes by moving one or more segments of the modified geometric routes in the IC design.
 19. The method of claim 9, wherein the post-processing operation modifies one or more geometric routes by defining additional segments and additional coordinates for one or more segments of the modified geometric routes in the IC design. 